Evaluation Printed Circuit Board

The Evaluation board for the CLC5956 allows for easy test

and evaluation of the product. The part may be ordered with

all components loaded and tested. The order number is the

CLC5956PCASM. The user supplies an analog input signal,

encode signal and power to the board and is able to take

latched 12-bit digital data out of the board.

ENCODE Input (ENC)

The ENCODE input is an SMA connector with a 50

Ω termi-

nation. The signal is converted from single to differential and

its frequency is divided by four to produce a low jitter, sym-

metrical encode signal for the CLC5956. The user should

provide a sinusoidal or square wave signal of 10 dBm to

16 dBm amplitude at four times the converter’s desired

sample rate. It is recommended that the source be low jitter

to maintain best performance. The transformer will pass sig-

nals in the 40 MHz to 260 MHz range which allows sample

rates of 10 Msps to 65 Msps.

Clock Option

The CLC5956 board is configured for a 4x clock input to pro-

vide optimal performance with some (i.e., HP8662) synthe-

sizers. The HP8662 output has lower jitter above 160 MHz.

Using a 208 MHz clock to sample at 52 MHz minimizes the

effect of the synthesizer on the measurement.

To use a 1x clock, replace the divide-by-4 sine-to-PECL con-

verter (U4, MC10EL33D) with an MC10EL16D. The

MC10EL16D sine-to-PECL converter does not divide the

clock. This approach would be suitable for use with a synthe-

sizer that has optimal jitter performance at 52 MHz (i.e.,

HP8643 or HP8644).

The best ADC performance is obtained with a low-jitter crys-

tal oscillator module installed at Y1 on the evaluation board.

U4 should be replaced with an MC10EL16D. Placing the

clock source on the evaluation board reduces ground loop

issues and thus improves performance.

Analog Input (AIN)

The analog input is an SMA connector with a 50

Ω termina-

tion. The signal is converted from single to differential by a

transformer with a 5 MHz to 260 MHz bandwidth and ap-

proximately one dB loss. Full scale is approximately 11 dBm

or 2.2 V

input signal be low jitter, low noise and low distortion to allow

for proper test and evaluation of the CLC5956.

Supply Voltages (J1 pins 31 A&B

and 32 A&B)

The CLC5956PCASM is powered from a single 5V supply

connected from the referenced pins on the Eurocard con-

nector. The recommended supplies are low noise linear sup-

plies.

Digital Outputs (J1 pins 7A (MSB,

D11), 8B (D10) through 18B (LSB)

and 20B (Data Ready)

The digital outputs are provided on the Eurocard connector.

The outputs are buffered by 5V CMOS latches with 50

Ω se-

ries output resistors. The rising edge of Data Ready may be

used to clock the output data into data collection cards or

logic analyzers. The board has a location for the HP

01650-63203 termination adapter for HP 16500 logic analyz-

ers to simplify connection to the analyzer.

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