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CLC5956PCASM 数据表(PDF) 2 Page - National Semiconductor (TI) |
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CLC5956PCASM 数据表(HTML) 2 Page - National Semiconductor (TI) |
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2 / 10 page ![]() Pin Configuration Ordering Information CLC5956IMTD 48-Pin TSSOP CLC5956IMTDX 48-Pin TSSOP (Taped Reel) CLC5956PCASM Evaluation Board Pin Descriptions Pin Name Pin No. Description A IN A IN 13, 14 Differential input with a common mode voltage of +2.4V. The ADC full scale input is 1.024 V PP on each of the complimentary input signals. ENCODE ENCODE 9, 10 Differential clock where ENCODE initiates a new data conversion cycle on each rising edge. Logic for these inputs are a 50% duty cycle differential PECL signal. VCM 21 Internal common mode voltage reference. Nominally +2.4V. Can be used for the input common mode voltage. This voltage is derived from an internal bandgap reference. D0–D11 30–34, 39–45 Digital data outputs are CMOS and TTL compatible. D0 is the LSB and D11 is the MSB. MSB is inverted. Output coding is two’s complement. GND 1–4, 8, 11, 12, 15, 19, 20, 23–26, 35, 36, 47, 48 Circuit ground. +AV CC 5–7, 16–18, 22 +5V power supply for the analog section. Bypass to ground with a 0.1 µF capacitor. +DV CC 37, 38, 46 +5V power supply for the digital section. Bypass to ground with a 0.1 µF capacitor. DS015011-1 www.national.com 2 |
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