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CLC5957PCASM 数据表(PDF) 7 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 CLC5957PCASM
功能描述  12-bit, 70MSPS Broadband Monolithic A/D Converter
PDF  12 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

CLC5957PCASM 数据表(HTML) 7 Page - National Semiconductor (TI)

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Analog Inputs and Bias
Figure 1 depicts the analog input and bias scheme. Each
of the differential analog inputs are internally biased to a
nominal voltage of 2.40 volts DC through a 500
Ω resistor
to a low impedance buffer. This enables a simple
interface to a broadband RF transformer with a center-
tapped output winding that is decoupled to the analog
ground. If the application requires the inputs to be DC
coupled, the Vcm output can be used to establish the
proper common -mode input voltage for the ADC. The
Vcm voltage reference is generated from an internal
bandgap source that is very accurate and stable.
Figure 1: CLC5957 Bias Scheme
The Vcm output may also be used to power down the
ADC. When the Vcm pin is pulled above 3.5V, the internal
bias mirror is disabled and the total current is reduced to
less than 10mA. Figure 2 depicts how this function can
be used. The diode is necessary to prevent the logic gate
from altering the ADC bias value.
Figure 2: Power Shutdown Scheme
ENCODE Clock Inputs
The CLC5957’s differential input clock scheme is
compatible with all commonly used clock sources.
Although small differential and single-ended signals are
adequate, for best aperture jitter performance a low noise
differential clock with a high slew rate is preferred. As
depicted in Figure 3, both ENCODE clock inputs are
internally biased to VCC/2 though a pair of 5KΩ resistors.
The clock input buffer operates with any common-mode
voltage between the supply and ground.
Figure 3: CLC5957 ENCODE Clock Inputs
The internal bias resistors simplify the clock interface to
another center-tapped transformer as depicted in Figure
4. A low phase noise, RF synthesizer of moderate ampli-
tude (1 - 4Vpp) can drive the ADC through this interface.
Figure 4: Transfer Coupled Clock Scheme
Vcm
1.23V
Bandgap
Reference
ADC
Bias Mirror
2K
To T/H
and ADC
Ain
Ain
2.4V
+
-
500
500
Vref
5V CMOS
"1" = on
"0" = off
CLC5957
BJT Current Mirror
VCCA
GNDA
ENC
ENC
5k
5k
5k
5k
ENC
ENC
CLC5957
~
CLC5957 Applications



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