Preliminary Technical Data

AD9229

Rev. PrF | Page 11 of 15

Oct. 6, 2003

THEORY OF OPERATION

Analog Inputs

For best dynamic performance, the source impedances driving

VIN+ and VIN– should be matched such that common-mode

settling errors are symmetrical. These errors will be reduced by the

common-mode rejection of the A/D.

Voltage Reference

The AD9229 has a stable and accurate reference voltage on chip,

which sets the full-scale voltage at the analog input channels.

Internal reference mode is established by grounding the SENSE pin.

(Recommended decoupling capacitors shown below) The internal

reference can be bypassed by setting SENSE to AVDD and driving

VREF with an external 1V reference.

SENSE

ADC

CORE

SELECT

LOGIC

AD9229

VREF

VINB

VINA

REFB

REFT

0.1u F

10 uF

0.1uF

10 uF

0.1uF

0.1uF

0.5V

Internal Reference Mode Connection

Digital Outputs

The AD9229’s differential outputs conform to the ANSI-644 LVDS

standard. To set the LVDS bias current, place a resistor (RSET is

nominally equal to 3.6 kΩ) to ground at the LVDSBIAS pin. The

RSET resistor current (~ 1.2/RSET) is ratioed on-chip setting the

output current at each output equal to a nominal 3.5 mA. A 100 Ω

differential termination resistor placed at the LVDS receiver inputs

results in a nominal 350 mV swing at the receiver.

The AD9229’s LVDS outputs facilitate interfacing with LVDS

receivers in custom ASICs and FPGAs that have LVDS capability

for superior switching performance in noisy environments. Single

point-to-point net topologies are recommended with a 100 Ω

termination resistor as close to the receiver as possible. It is

recommended to keep the trace length no longer than 1–2 inches

and to keep differential output trace lengths as equal as possible.

The format of the output data is offset binary.

Timing

Data from each A/D is serialized and provided on a separate

channel.

Two output clocks are provided to assist in capturing data from the

AD9229. The data clock out (DCO) is used to clock the output

data and is equal to 6 times the sample clock frequency. ( 390MHz

for 65MHz input clock) Data is clocked out of the AD9229 on the

rising and falling edges of DCO. The FCO clock signals the start of

a new serial word, the rising edge of FCO occurs at the start of an

MSB.

PLL

The AD9229 contains an internal PLL that is used to generate

internal clocking signals, if the PLL is unlocked, the data outputs

are static.