COP884CF datasheet(21/44 Pages) NSC

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Multi-Input Wakeup (Continued)

The GIE (global interrupt enable) bit enables the interrupt

function. A control flag, LPEN, functions as a global interrupt

enable for Port L interrupts. Setting the LPEN flag will enable

interrupts and vice versa. A separate global pending flag is

not needed since the register WKPND is adequate.

Since Port L is also used for waking the device out of the

HALT or IDLE modes, the user can elect to exit the HALT or

IDLE modes either with or without the interrupt enabled. If he

elects to disable the interrupt, then the device will restart ex-

ecution from the instruction immediately following the in-

struction that placed the microcontroller in the HALT or IDLE

modes. In the other case, the device will first execute the in-

terrupt service routine and then revert to normal operation.

The Wakeup signal will not start the chip running immedi-

ately since crystal oscillators or ceramic resonators have a fi-

nite start up time. The IDLE Timer (T0) generates a fixed de-

lay to ensure that the oscillator has indeed stabilized before

allowing the device to execute instructions. In this case,

upon detecting a valid Wakeup signal, only the oscillator cir-

cuitry and the IDLE Timer T0 are enabled. The IDLE Timer is

loaded with a value of 256 and is clocked from the t

c instruc-

tion cycle clock. The t

c clock is derived by dividing down the

oscillator clock by a factor of 10. A Schmitt trigger following

the CKI on-chip inverter ensures that the IDLE timer is

clocked only when the oscillator has a sufficiently large am-

plitude to meet the Schmitt trigger specifications. This

Schmitt trigger is not part of the oscillator closed loop. The

startup timeout from the IDLE timer enables the clock signals

to be routed to the rest of the chip.

If the RC clock option is used, the fixed delay is under soft-

ware control. A control flag, CLKDLY, in the G7 configuration

bit allows the clock start up delay to be optionally inserted.

Setting CLKDLY flag high will cause clock start up delay to

be inserted and resetting it will exclude the clock start up de-

lay. The CLKDLY flag is cleared during reset, so the clock

start up delay is not present following reset with the RC clock

options.

A/D Converter

The device contains an 8-channel, multiplexed input, suc-

cessive approximation, A/D converter. Two dedicated pins,

REFand AGND are provided for voltage reference.

OPERATING MODES

The A/D converter supports ratiometric measurements. It

supports both Single Ended and Differential modes of opera-

tion.

Four specific analog channel selection modes are sup-

ported. These are as follows:

Allow any specific channel to be selected at one time. The

A/D converter performs the specific conversion requested

and stops.

Allow any specific channel to be scanned continuously. In

other words, the user will specify the channel and the A/D

converter will keep on scanning it continuously. The user can

come in at any arbitrary time and immediately read the result

of the last conversion. The user does not have to wait for the

current conversion to be completed.

Allow any differential channel pair to be selected at one time.

The A/D converter performs the specific differential conver-

sion requested and stops.

Allow any differential channel pair to be scanned continu-

ously. In other words, the user will specify the differential

channel pair and the A/D converter will keep on scanning it

continuously. The user can come in at any arbitrary time and

immediately read the result of the last differential conversion.

The user does not have to wait for the current conversion to

be completed.

The A/D converter is supported by two memory mapped reg-

isters, the result register and the mode control register.

When the device is reset, the control register is cleared and

the A/D is powered down. The A/D result register has un-

known data following reset.

DS009425-16

FIGURE 11. Multi-Input Wake Up Logic

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