ICS8516 datasheet(9/15 Pages) ICST

9 / 15 page

8516FY

www.icst.com/products/hiperclocks.html

REV. B FEBRUARY 21, 2006

Integrated

Circuit

Systems, Inc.

ICS8516

LOW SKEW, 1-TO-16

DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

APPLICATION INFORMATION

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V

DD/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V

DD= 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

V_REF

0.1u

Single Ended Clock Input

CLKx

nCLKx

VDD

INPUTS:

LVCMOS CONTROL PINS:

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1k

Ω resistor can be used.

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

OUTPUTS:

LVDS – Like OUTPUT

All unused LVDS output pairs can be either left floating or

terminated with 100

Ω across. If they are left floating, we

recommend that there is no trace attached.

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