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MPC870 数据表(PDF) 40 Page - Freescale Semiconductor, Inc |
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MPC870 数据表(HTML) 40 Page - Freescale Semiconductor, Inc |
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40 / 84 page  MPC875/MPC870 Hardware Specifications, Rev. 3.0 40 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 13 shows the PCMCIA port timing for the MPC875/870. Figure 29 provides the PCMCIA output port timing for the MPC875/870. Figure 29. PCMCIA Output Port Timing Figure 30 provides the PCMCIA input port timing for the MPC875/870. Figure 30. PCMCIA Input Port Timing Table 13. PCMCIA Port Timing Num Characteristic 33 MHz 40 MHz 66 MHz 80 MHz Unit Min Max Min Max Min Max Min Max P57 CLKOUT to OPx valid (MAX = 0.00 × B1 + 19.00) — 19.00 — 19.00 — 19.00 — 19.00 ns P58 HRESET negated to OPx drive 1(MIN = 0.75 × B1 + 3.00) 1 OP2 and OP3 only. 25.70 — 21.70 — 14.40 — 12.40 — ns P59 IP_Xx valid to CLKOUT rising edge (MIN = 0.00 × B1 + 5.00) 5.00 — 5.00 — 5.00 — 5.00 — ns P60 CLKOUT rising edge to IP_Xx invalid (MIN = 0.00 × B1 + 1.00) 1.00 — 1.00 — 1.00 — 1.00 — ns CLKOUT HRESET Output Signals OP2, OP3 P57 P58 CLKOUT Input Signals P59 P60 |
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