MSP430F435IPZ datasheet(21/85 Pages) TI

21 / 85 page

MSP430x43x, MSP430x44x

MIXED SIGNAL MICROCONTROLLER

SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

flash memory, control register FCTL1, FCTL2, and FCTL3 (continued)

rw–0

SEG

WRT

res.

MEras Erase

res.

rw–0r–0r–0r–0rw–0rw–0r–0

096h

0A5h

FCTL1

0128h

FCTL1 Read:

FCTL1 Write:

The bits control erase or mass erase of the flash, write (WRT), programming, or segment write (SEGWRT).

The control register FCTL2 determines the operation of the timing generator that generates all the timing signals

necessary for write, erase, and mass erase from the selected clock source. One of three different clock sources

may be selected. The selected clock source must be divided to meet the frequency requirements specified in

the recommended operating conditions.

NOTE:

The mass erase duration generated by the flash timing generator is at least 11.1 ms. The cumulative

mass erase time needed is 200 ms. This can be achieved by repeating the mass erase operation

until the cumulative mass erase time is met (a minimum of 19 cycles may be required).

rw–0

SSEL1

FN5

rw–1rw–0rw–1

096h

0A5h

FCTL2

012Ah

FCTL2 Read:

FCTL2 Write:

SSEL0

FN4

FN3

FN2

FN1

FN0

rw–0rw–0rw–0rw–0

Control register FCTL3 determines the access and flags the status and error conditions of the flash operation.

There are no restrictions to modify this control register. Control bits are reset or set (WAIT) with PUC but key

violation bit KEYV is reset with POR.

rw–1

ACCV

IFG

EMEX

res.

WAIT

KEYV

BUSY

rw–0

r–0r–0r–1rw–0rw–(0)

096h

0A5h

FCTL3

012Ch

FCTL3 Read:

FCTL3 Write:

Lock

r(w)–0

MSP430F435IPZ 数据表(PDF) 21 Page - Texas Instruments

MSP430F435IPZ 数据表(HTML) 21 Page - Texas Instruments

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MSP430F435IPZ 数据表(PDF) 21 Page - Texas Instruments

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