COP8SCR9 datasheet(39/80 Pages) NSC

39 / 80 page

13.0 Power Saving Features

(Continued)

13.2 OSCILLATOR STABILIZATION

Both the high speed oscillator and low speed oscillator have

a startup delay associated with them. When switching be-

tween the modes, the software must ensure that the appro-

priate oscillator is started up and stabilized before switching

to the new mode. See Table 3, Startup Times for approxi-

mate startup times for both oscillators.

13.3 HIGH SPEED MODE OPERATION

This mode of operation allows high speed operation for both

the main Core clock and also for the Idle Timer. This is the

default mode of the device and will always be entered upon

any of the Reset conditions described in the Reset section. It

can also be entered from Dual Clock mode. It cannot be

directly entered from the Low Speed mode without passing

through the Dual Clock mode first.

To enter from the Dual Clock mode, the following sequence

must be followed using two separate instructions:

Software clears DCEN to 0.

Software clears LSON to 0.

13.3.1 High Speed Halt Mode

The fully static architecture of this device allows the state of

the microcontroller to be frozen. This is accomplished by

stopping the internal clock of the device during the HALT

mode. The controller also stops the CKI pin from oscillating

during the HALT mode. The processor can be forced to exit

the HALT mode and resume normal operation at any time.

During normal operation, the actual power consumption de-

pends heavily on the clock speed and operating voltage

used in an application and is shown in the Electrical Speci-

fications. In the HALT mode, the device only draws a small

leakage current, plus current for the BOR feature (if en-

abled), plus any current necessary for driving the outputs.

Since total power consumption is affected by the amount of

current required to drive the outputs, all I/Os should be

configured to draw minimal current prior to entering the

HALT mode, if possible. In order to reduce power consump-

tion even further, the power supply (V

CC) can be reduced to

a very low level during the HALT mode, just high enough to

guarantee retention of data stored in RAM. The allowed

lower voltage level (V

R) is specified in the Electrical Specs

section.

13.3.1.1 Entering The High Speed Halt Mode

The device enters the HALT mode under software control

when the Port G data register bit 7 is set to 1. All processor

action stops in the middle of the next instruction cycle, and

power consumption is reduced to a very low level.

13.3.1.2 Exiting The High Speed Halt Mode

There is a choice of methods for exiting the HALT mode: a

chip Reset using the RESET pin or a Multi-Input Wake-up.

13.3.1.3 HALT Exit Using Reset

A device Reset, which is invoked by a low-level signal on the

RESET input pin, takes the device out of the HALT mode

and starts execution from address 0000H. The initialization

software should determine what special action is needed, if

any, upon start-up of the device from HALT. The initialization

of all registers following a RESET exit from HALT is de-

scribed in the Reset section of this manual.

13.3.1.4 HALT Exit Using Multi-Input Wake-up

The device can be brought out of the HALT mode by a

transition received on one of the available Wake-up pins.

The pins used and the types of transitions sensed on the

Multi-input pins are software programmable. For information

on programming and using the Multi-Input Wake-up feature,

refer to the Multi-Input Wake-up section.

A start-up delay is required between the device wake-up and

the execution of program instructions, depending on the type

of chip clock. The start-up delay is mandatory, and is imple-

mented whether or not the CLKDLY bit is set. This is be-

cause all crystal oscillators and resonators require some

time to reach a stable frequency and full operating ampli-

tude.

The IDLE Timer (Timer T0) provides a fixed delay from the

time the clock is enabled to the time the program execution

begins. Upon exit from the HALT mode, the IDLE Timer is

enabled with a starting value of 256 and is decremented with

each instruction cycle. (The instruction clock runs at one-fifth

the frequency of the high speed oscillator.) An internal

Schmitt trigger connected to the on-chip CKI inverter en-

sures that the IDLE Timer is clocked only when the oscillator

has a large enough amplitude. (The Schmitt trigger is not

part of the oscillator closed loop.) When the IDLE Timer

underflows, the clock signals are enabled on the chip, allow-

ing program execution to proceed. Thus, the delay is equal

to 256 instruction cycles.

Note: To ensure accurate operation upon start-up of the

device using Multi-Input Wake-up, the instruction in the ap-

plication program used for entering the HALT mode should

be followed by two consecutive NOP (no-operation) instruc-

tions.

13.3.1.5 Options

This device has two options associated with the HALT mode.

The first option enables the HALT mode feature, while the

second option disables HALT mode operation. Selecting the

disable HALT mode option will cause the microcontroller to

ignore any attempts to HALT the device under software

control. Note that this device can still be placed in the HALT

mode by stopping the clock input to the microcontroller, if the

program memory is masked ROM. See the Option section

for more details on this option bit.

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