COP8SCR9 datasheet(19/80 Pages) NSC

19 / 80 page

9.0 Pin Descriptions (Continued)

10.0 Functional Description

The architecture of the device is a modified Harvard archi-

tecture. With the Harvard architecture, the program memory

(Flash) is separate from the data store memory (RAM). Both

Program Memory and Data Memory have their own separate

addressing space with separate address buses. The archi-

tecture, though based on the Harvard architecture, permits

transfer of data from Flash Memory to RAM.

10.1 CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or shift

operation in one instruction (t

C) cycle time.

There are six CPU registers:

A is the 8-bit Accumulator Register

PC is the 15-bit Program Counter Register

PU is the upper 7 bits of the program counter (PC)

PL is the lower 8 bits of the program counter (PC)

B is an 8-bit RAM address pointer, which can be optionally

post auto incremented or decremented.

X is an 8-bit alternate RAM address pointer, which can be

optionally post auto incremented or decremented.

S is the 8-bit Data Segment Address Register used to extend

the lower half of the address range (00 to 7F) into 256 data

segments of 128 bytes each.

SP is the 8-bit stack pointer, which points to the subroutine/

interrupt stack (in RAM). With reset the SP is initialized to

RAM address 06F Hex. The SP is decremented as items are

pushed onto the stack. SP points to the next available loca-

tion on the stack.

All the CPU registers are memory mapped with the excep-

tion of the Accumulator (A) and the Program Counter (PC).

10.2 PROGRAM MEMORY

The program memory consists of 32,768 bytes of Flash

Memory. These bytes may hold program instructions or con-

stant data (data tables for the LAID instruction, jump vectors

for the JID instruction, and interrupt vectors for the VIS

instruction). The program memory is addressed by the 15-bit

program counter (PC). All interrupts in the device vector to

program memory location 00FF Hex. The program memory

reads 00 Hex in the erased state. Program execution starts

at location 0 after RESET.

If a Return instruction is executed when the SP contains 6F

(hex), instruction execution will continue from Program

Memory location 7FFF (hex). If location 7FFF is accessed by

an instruction fetch, the Flash Memory will return a value of

00. This is the opcode for the INTR instruction and will cause

a Software Trap.

For the purpose of erasing and rewriting the Flash Memory,

it is organized in pages of 128 bytes.

10.3 DATA MEMORY

The data memory address space includes the on-chip RAM

and data registers, the I/O registers (Configuration, Data and

Pin), the control registers, the MICROWIRE/PLUS SIO shift

with the timers and the USART (with the exception of the

IDLE timer). Data memory is addressed directly by the in-

struction or indirectly by the B, X and SP pointers.

The data memory consists of 1024 bytes of RAM. Sixteen

bytes of RAM are mapped as “registers” at addresses 0F0 to

0FF Hex. These registers can be loaded immediately, and

also decremented and tested with the DRSZ (decrement

registers X, SP, B and S are memory mapped into this space

at address locations 0FC to 0FF Hex respectively, with the

other registers being available for general usage.

The instruction set permits any bit in memory to be set, reset

or tested. All I/O and registers (except A and PC) are

memory mapped; therefore, I/O bits and register bits can be

directly and individually set, reset and tested. The accumu-

lator (A) bits can also be directly and individually tested.

Note: RAM contents are undefined upon power-up.

10.4 DATA MEMORY SEGMENT RAM EXTENSION

Data memory address 0FF is used as a memory mapped

location for the Data Segment Address Register (S).

The data store memory is either addressed directly by a

single byte address within the instruction, or indirectly rela-

tive to the reference of the B, X, or SP pointers (each

contains a single-byte address). This single-byte address

allows an addressing range of 256 locations from 00 to FF

hex. The upper bit of this single-byte address divides the

data store memory into two separate sections as outlined

previously. With the exception of the RAM register memory

from address locations 00F0 to 00FF, all RAM memory is

memory mapped with the upper bit of the single-byte ad-

dress being equal to zero. This allows the upper bit of the

single-byte address to determine whether or not the base

address range (from 0000 to 00FF) is extended. If this upper

bit equals one (representing address range 0080 to 00FF),

then address extension does not take place. Alternatively, if

this upper bit equals zero, then the data segment extension

0000 to 007F) from XX00 to XX7F, where XX represents the

8 bits from the S register. Thus the 128-byte data segment

extensions are located from addresses 0100 to 017F for

data segment 1, 0200 to 027F for data segment 2, etc., up to

FF00 to FF7F for data segment 255. The base address

range from 0000 to 007F represents data segment 0.

10138909

FIGURE 6. Emulation Connection

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