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CPC7591 数据表(PDF) 13 Page - IXYS Corporation |
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CPC7591 数据表(HTML) 13 Page - IXYS Corporation |
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13 / 17 page ![]() INTEGRATED CIRCUITS DIVISION CPC7591 R06 www.ixysic.com 13 2.4 Data Latch The CPC7591 has an integrated transparent data latch. The latch enable operation is controlled by TTL logic input levels at the LATCH pin. Data input to the latch is via the input pin INRINGING, while the output of the data latch are internal nodes used for state control. When the LATCH enable control pin is at logic 0 the data latch is transparent and the INRINGING input data control signal flows directly through the data latch to the state control circuitry. A change in INRINGING input will be reflected by a change in switch state. Whenever the LATCH enable control pin is at logic 1, the data latch is active and data is locked. Subsequent INRINGING input changes will not result in a change to the control logic or affect the existing switch state. The switches will remain in the state they were in when the LATCH pin changes from logic 0 to logic 1 and will not respond to changes in input as long as the LATCH is at logic 1. However, neither the TSD input nor the TSD output control functions are affected by the latch function. Since internal thermal shutdown control and external “All-off” control is not affected by the state of the LATCH enable input, TSD will override state control. 2.5 TSD Pin Description The TSD pin is a bi-directional I/O structure with an internal pull-up current source with a nominal value of 16 A biased from V DD. As an output, this pin indicates the status of the thermal shutdown circuitry. Typically, during normal operation, this pin will be pulled up to VDD but under fault conditions that create excess thermal loading the CPC7591 will enter thermal shutdown and a logic low will be output. As an input, the TSD pin is utilized to place the CPC7591 into the “All-Off” state by simply pulling the input low. For applications using low-voltage logic devices (lower than VDD), IXYS IC Division recommends the use of an open-collector or an open-drain type output to control TSD. This avoids sinking the TSD pull up bias current to ground during normal operation when the all-off state is not required. An open-collector or open-drain type device is recommended to drive this pin. 2.6 Ringing Switch Zero-Cross Current Turn Off After the application of a logic input to turn SW4 off, the ringing switch is designed to delay the change in state until the next zero-crossing. Once on, the switch requires a zero-current cross to turn off, and therefore should not be used to switch a pure DC signal. The switch will remain in the on state no matter the logic input until the next zero crossing. These switching characteristics will reduce and possibly eliminate overall system impulse noise normally associated with ringing switches. See IXYS IC Division’s application note AN-144, Impulse Noise Benefits of Line Card Access Switches for more information. The attributes of ringing switch SW4 may make it possible to eliminate the need for a zero-cross switching scheme. A minimum impedance of 300 in series with the ringing generator is recommended. 2.7 Power Supplies Both a +5 V supply and battery voltage are connected to the CPC7591. Switch state control is powered exclusively by the +5 V supply. As a result, the CPC7591 exhibits extremely low power consumption during active and idle states. Although battery power is not used for switch control, it is required to supply trigger current for the integrated internal protection circuitry SCR during fault conditions. This integrated SCR is designed to activate whenever the voltage at TBAT or RBAT drops 2 to 4 V below the applied voltage on the VBAT pin. Because the battery supply at this pin is required to source trigger current during negative overvoltage fault conditions at tip and ring, it is important that the net supplying this current be a low impedance path for high speed transients such as lightning. This will permit trigger currents to flow enabling the SCR to activate and thereby prevent a fault induced negative overvoltage event at the TBAT or RBAT nodes. 2.8 Battery Voltage Monitor The CPC7591 also uses the VBAT pin to monitor battery voltage. If system battery voltage is lost, the CPC7591 immediately enters the all-off state. It remains in this state until the battery voltage is restored. The device also enters the all-off state if the system battery voltage goes more positive than –10 V, |
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