BQ20Z95_14 datasheet(9/21 Pages) TI1

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bq20z95

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SLUS757C – JULY 2007 – REVISED OCTOBER 2013

DATA FLASH CHARACTERISTICS (Over Recommended Operating Temperature and Supply

Voltage) (continued)

Typical Values at TA = 25°C and V(REG25) = 2.5 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Data retention

Years

Flash programming write-cycles

20k

Cycles

t(ROWPROG)

Row programming time

See (1)

t(MASSERASE) Mass-erase time

200

t(PAGEERASE) Page-erase time

I(DDPROG)

Flash-write supply current

I(DDERASE)

Flash-erase supply current

RAM BACKUP

V(RBI) > V(RBI)MIN, VREG25 < VIT–,

1000

2500

TA = 85°C

I(RB)

RB data-retention input current

V(RBI) > V(RBI)MIN, VREG25 < VIT–,

220

TA = 25°C

V(RB)

RB data-retention input voltage(1)

1.7

(1)

Specified by design. Not production tested.

SMBUS TIMING CHARACTERISTICS

TA = –40°C to 85°C Typical Values at TA = 25°C and VREG25 = 2.5 V (Unless Otherwise Noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f(SMB)

SMBus operating frequency

SLAVE mode, SMBC 50% duty cycle

100

kHz

f(MAS)

SMBus master clock frequency

MASTER mode, No clock low slave extend

51.2

kHz

Bus free time between start and stop

t(BUF)

4.7

µs

(see Figure 1)

t(HD:STA)

Hold time after (repeated) start (see

µs

Figure 1)

t(SU:STA)

Repeated start setup time (see Figure 1)

4.7

µs

t(SU:STO)

Stop setup time (see Figure 1)

µs

t(HD:DAT)

RECEIVE mode

Data hold time (see Figure 1)

TRANSMIT mode

300

t(SU:DAT)

Data setup time (see Figure 1)

250

t(TIMEOUT)

Error signal/detect (see Figure 1)

See (1)

µs

t(LOW)

Clock low period (see Figure 1)

4.7

µs

t(HIGH)

Clock high period (see Figure 1)

See (2)

µs

t(LOW:SEXT) Cumulative clock low slave extend time

See (3)

µs

Cumulative clock low master extend time

t(LOW:MEXT)

See (4)

µs

(see Figure 1)

Clock/data fall time

See (5)

300

Clock/data rise time

See (6)

1000

(1)

The bq20z95 times out when any clock low exceeds t(TIMEOUT).

(2)

t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving bq20z95 that is in

progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0).

(3)

t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.

(4)

t(LOW:MEXT) is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.

(5)

Rise time tr = VILMAX – 0.15) to (VIHMIN + 0.15)

(6)

Fall time tf = 0.9VDD to (VILMAX – 0.15)

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