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DP83266 数据表(PDF) 39 Page - National Semiconductor (TI) |
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DP83266 数据表(HTML) 39 Page - National Semiconductor (TI) |
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39 / 152 page  60 Functional Description (Service Engine) (Continued) Tmmu Host MMU performs an address translation during this clock Tpa Host MMU drives AB AD with the address Td MACSI device negates AB AS asserts AB DEN drives AB AD with the write data and starts sampling AB ACK and AB ERR Slave captures AB AD data as- serts AB ACK and drives AB ERR MACSI device sam- ples a valid AB ACK Tw states may occur after Td Tr MACSI device negates AB RW AB DEN and AB SIZ 20 and releases AB A AB AD and AB AS Slave deasserts AB ACK and AB ERR and stops driving AB AD with data Burst Read Tbr MACSI device asserts AB BR to indicate it wishes to perform a transfer Host asserts AB BG The MACSI de- vice moves to Tva within the next three clocks and then drives AB A and AB AD Tva MACSI device drives AB A and AB AD with the vir- tual address for one clock negates AB AS asserts AB RW drives AB SIZ 20 and negates AB BR if an- other transaction is not required Tmmu Host MMU performs an address translation during this clock Tpa Host MMU drives AB AD with the translated (physi- cal) address Td MACSI device asserts AB DEN and samples AB ACK and AB ERR Slave asserts AB ACK drives AB ERR and drives AB AD (with data) when ready MACSI device samples a valid AB ACK and captures the read data Tw states may occur after Td This state is re- peated four or eight times (according to burst size) If SIMR1ASM e 0 the MACSI device negates AB AS in the last Td cycle If SIMR1ASM e 1 the MACSI device will negate AB AS in the first Td cycle Tr MACSI device negates AB RW AB DEN and AB SIZ 20 and releases AB A and AB AS Slave deasserts AB ACK and AB ERR and releases AB AD Burst Write Tbr MACSI device asserts AB BR to indicate it wishes to perform a transfer Host asserts AB BG The MACSI de- vice moves to Tva within the next three clocks and then drives AB A and AB AD Tva MACSI device drives AB A and AB AD with the vir- tual address for one clock negates AB AS negates AB RW drives AB SIZ 20 Tmmu Host MMU performs an address translation during this clock Tpa Host MMU drives AB AD with the address Td MACSI device asserts AB DEN drives AB AD with the write data and starts sampling AB ACK and AB ERR Slave captures AB AD data asserts AB ACK and drives AB ERR MACSI device samples a valid AB ACK Tw states may occur after Td Td is repeated as required for the complete burst If SIMR1ASM e 0 the MACSI device negates AB AS in the last Td cycle If SIMR1ASM e 1 the MACSI device will negate AB AS in the first Td cycle Tr MACSI device negates AB RW AB DEN and AB SIZ 20 releases AB A AB AD and AB AS and stops driving AB AD with data Slave deasserts AB ACK and AB ERR 65 ENHANCED ABUS MODE When the enhanced ABus mode is selected several chang- es occur The timing of AB ACK is modified during read accesses In this mode read data is expected one cycle after the AB ACK signal (see Figure 6-8 and Figure 6-11 ) In addition channel information is no longer supplied on the upper four bits of the AddressData lines during the address cycle Instead the value of this nibble of address is supplied from a programmable register within the MACSI device (for a full description of these bits please see System Interface Mode Register1 (SIMR1)) Finally the AB DEN signal be- comes an input in this enhanced mode This signal along with AB ACK and AB ERR are used to encode a subset of the acknowledge retry and error functions supported on the SBus These enhancements make it easier to connect the MACSI device to the SBus as a bus master However a full FDDI adapter design requires the design of a slave interface from the SBus to the control bus of the MACSI device and the other FDDI components 651 Enhanced ABus Mode Bus Transactions Bus transactions in the Enhanced Abus Mode are shown in Figure 6-8 through Figure 6-11 In the Enhanced ABus mode the Bus Request signal (AB BR) will be deasserted after the bus is granted until the completion of the bus trans- action The only exception to this may occur when the MACSI device is attempting back-to-back burst reads In this case AB BR may be deasserted for as few as two cycles Single Read Tbr MACSI device asserts AB BR to indicate it wishes to perform a transfer Host asserts AB BG The MACSI de- vice moves to Tma on the next cycle Tma MACSI device drives AB A and AB AD with the master address asserts AB AS drives AB RW and AB SIZ 20 and negates AB BR until the end of this transaction Tpa The Physical address is asserted by the MMU Td MACSI device negates AB AS and samples AB ACK AB ERR and AB DEN Slave asserts AB ACK AB ERR and AB DEN with the appropriate acknowledg- ment The MACSI device samples a valid acknowledgment and moves to Tr Tw states may occur after Td Tr MACSI device negates AB RW AB DEN and AB SIZ 20 releases AB A and AB AS and samples AB AD Slave drives AB AD (with data) deasserts AB ACK AB ERR and AB DEN and releases AB AD 39 |
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