DP83846 datasheet(6/59 Pages) NSC

6 / 59 page

www.national.com

1.2 10 Mb/s and 100 Mb/s PMD Interface

RX_CLK

O, PU

RECEIVE CLOCK: Provides the 25 MHz recovered receive

clocks for 100BASE-TX mode and 2.5 MHz for 10BASE-T

nibble mode.

RXD[3]

RXD[2]

RXD[1]

RXD[0]

O, PU/PD 38, 39, 40,

RECEIVE DATA: Nibble wide receive data (synchronous to

corresponding RX_CLK, 25 MHz for 100BASE-TX mode,

2.5 MHz for 10BASE-T nibble mode). Data is driven on the

falling edge of RX_CLK. RXD[2] has an internal pulldown re-

sistor. The remaining RXD pins have pullups.

RX_ER/PAUSE_EN

S, O, PU

RECEIVE ERROR: Asserted high to indicate that an invalid

symbol has been detected within a received packet in

100BASE-TX mode.

RX_DV

RECEIVE DATA VALID: Asserted high to indicate that valid

data is present on the corresponding RXD[3:0] for nibble

mode. Data is driven on the falling edge of the correspond-

ing RX_CLK.

Signal Name

Type

Pin #

Description

TD+, TD-

16, 17

Differential common driver transmit output. These differen-

tial outputs are configurable to either 10BASE-T or

100BASE-TX signaling.

The DP83846A will automatically configure the common

driver outputs for the proper signal type as a result of either

forced configuration or Auto-Negotiation.

RD-, RD+

10, 11

Differential receive input. These differential inputs can be

configured to accept either 100BASE-TX or 10BASE-T sig-

naling.

The DP83846A will automatically configure the receive in-

puts to accept the proper signal type as a result of either

forced configuration or Auto-Negotiation.

Signal Name

Type

Pin #

Description

DP83846 数据表(PDF) 6 Page - National Semiconductor (TI)

DP83846 数据表(HTML) 6 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

数据表下载