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3.3.9 4B/5B Decoder

The code-group decoder functions as a look up table that

translates incoming 5B code-groups into 4B nibbles. The

code-group decoder ﬁrst detects the J/K code-group pair

preceded by IDLE code-groups and replaces the J/K with

MAC preamble. Speciﬁcally, the J/K 10-bit code-group pair

is replaced by the nibble pair (0101 0101). All subsequent

5B code-groups are converted to the corresponding 4B

nibbles for the duration of the entire packet. This conver-

sion ceases upon the detection of the T/R code-group pair

denoting the End of Stream Delimiter (ESD) or with the

reception of a minimum of two IDLE code-groups.

3.3.10 100BASE-TX Link Integrity Monitor

The 100 Base TX Link monitor ensures that a valid and sta-

ble link is established before enabling both the Transmit

and Receive PCS layer.

Signal detect must be valid for 395us to allow the link mon-

itor to enter the 'Link Up' state, and enable the transmit and

receive functions.

3.3.11 Bad SSD Detection

A Bad Start of Stream Delimiter (Bad SSD) is any transition

from consecutive idle code-groups to non-idle code-groups

which is not preﬁxed by the code-group pair /J/K.

If this condition is detected, the DP83846A will assert

RX_ER and present RXD[3:0] = 1110 to the MII for the

cycles that correspond to received 5B code-groups until at

least two IDLE code groups are detected. In addition, the

False Carrier Sense Counter register (FCSCR) will be

incremented by one.

Once at least two IDLE code groups are detected, RX_ER

and CRS become de-asserted.

3.4 10BASE-T TRANSCEIVER MODULE

The 10BASE-T Transceiver Module is IEEE 802.3 compli-

ant. It includes the receiver, transmitter, collision, heart-

beat, loopback, jabber, and link integrity functions, as

deﬁned in the standard. An external ﬁlter is not required on

the 10BASE-T interface since this is integrated inside the

DP83846A. This section focuses on the general 10BASE-T

system level operation.

3.4.1 Operational Modes

The DP83846A has two basic 10BASE-T operational

modes:

— Half Duplex mode

— Full Duplex mode

Half Duplex Mode

In Half Duplex mode the DP83846A functions as a stan-

dard IEEE 802.3 10BASE-T transceiver supporting the

CSMA/CD protocol.

Full Duplex Mode

In Full Duplex mode the DP83846A is capable of simulta-

neously transmitting and receiving without asserting the

collision signal. The DP83846A's 10 Mb/s ENDEC is

designed to encode and decode simultaneously.

3.4.2 Collision Detection and SQE

When in Half Duplex, a 10BASE-T collision is detected

when the receive and transmit channels are active simulta-

neously. Collisions are reported by the COL signal on the

MII. Collisions are also reported when a jabber condition is

detected.

The COL signal remains set for the duration of the collision.

If the ENDEC is receiving when a collision is detected it is

reported immediately (through the COL pin).

When heartbeat is enabled, approximately 1

µs after the

transmission of each packet, a Signal Quality Error (SQE)

signal of approximately 10-bit times is generated to indicate

successful transmission. SQE is reported as a pulse on the

COL signal of the MII.

The SQE test is inhibited when the PHY is set in full duplex

mode.

SQE

can

also

inhibited

setting

the

HEARTBEAT_DIS bit in the 10BTSCR register.

3.4.3 Carrier Sense

Carrier Sense (CRS) may be asserted due to receive activ-

ity once valid data is detected via the squelch function.

For 10 Mb/s Half Duplex operation, CRS is asserted during

either packet transmission or reception.

For 10 Mb/s Full Duplex operation, CRS is asserted only

during receive activity.

CRS is deasserted following an end of packet.

3.4.4 Normal Link Pulse Detection/Generation

The link pulse generator produces pulses as deﬁned in the

IEEE 802.3 10BASE-T standard. Each link pulse is nomi-

nally 100 ns in duration and transmitted every 16 ms in the

absence of transmit data.

Link pulses are used to check the integrity of the connec-

tion with the remote end. If valid link pulses are not

received, the link detector disables the 10BASE-T twisted

pair transmitter, receiver and collision detection functions.

When

the

link

integrity

function

disabled

(FORCE_LINK_10 of the 10BTSCR register), good link is

forced and the 10BASE-T transceiver will operate regard-

less of the presence of link pulses.

3.4.5 Jabber Function

The jabber function monitors the DP83846A's output and

disables the transmitter if it attempts to transmit a packet of

longer than legal size. A jabber timer monitors the transmit-

ter and disables the transmission if the transmitter is active

beyond the Jab time (20-150 ms).

Once disabled by the Jabber function, the transmitter stays

disabled for the entire time that the ENDEC module's inter-

nal transmit enable is asserted. This signal has to be de-

asserted for approximately 250-750 ms (the “unjab” time)

before the Jabber function re-enables the transmit outputs.

The Jabber function is only relevant in 10BASE-T mode.

3.4.6 Automatic Link Polarity Detection and Correction

The DP83846A's 10BASE-T transceiver module incorpo-

rates an automatic link polarity detection circuit. When

seven consecutive inverted link pulses are received,

inverted polarity is reported.

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