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DRV10983ZPWPR 数据表(PDF) 45 Page - Texas Instruments |
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DRV10983ZPWPR 数据表(HTML) 45 Page - Texas Instruments |
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45 / 58 page ![]() 45 DRV10983 www.ti.com SLVSCP6C – JULY 2014 – REVISED MAY 2016 Product Folder Links: DRV10983 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Table 9. Register Description (continued) Register Data Description Name Address Bits SysOpt6(3) 0x28 7:4 SWiLimitThr [3:0] Acceleration current limit threshold 0000 = No acceleration current limit 0001 = 0.2-A current limit xxxx = n × 0.2 A current limit 3:1 HWiLimitThr [2:0] Lock detection current limit threshold (n + 1) × 0.4 A 0 N/A N/A SysOpt7(3) 0x29 7 LockEn[5] Stuck in closed loop (no zero cross detected). Enabled when high 6:4 ClsLpAccel[2:0] Closed loop accelerate 000 = Inf fast 001 = 48 VCC/s 010 = 48 VCC/s 011 = 0.77 VCC/s 100 = 0.37 VCC/s 101 = 0.19 VCC/s 110 = 0.091 VCC/s 111 = 0.045 VCC/s 3:0 Deadtime[3:0] Dead time between HS and LS gate drive for motor phases 0000 = 40 ns xxxx = (n + 1) × 40 ns SysOpt8(3) 0x2A 7:4 IPDCurrThr[3:0] IPD (inductive sense) current threshold 0000 = No IPD function. Align and Go 0001 = 0.4-A current threshold. xxxx = 0.2 A × (n + 1) current threshold. 3 LockEn[4] Open loop stuck (no zero cross detected). Enabled when high 2 VregSel Buck regulator voltage select 0: Vreg = 5 V 1: Vreg = 3.3 V 1:0 IPDClk[1:0] Inductive sense clock 00 = 12 Hz; 01 = 24 Hz; 10 = 47 Hz; 11 = 95 Hz SysOpt9(3) 0x2B 7:6 FGOLSel[1:0] FG open loop output select 00 = FG outputs in both open loop and closed loop 01 = FG outputs only in closed loop 10 = FG outputs closed loop and the first open loop 11 = Reserved 5:4 FGcycle[1:0] FG cycle select 00 = 1 pulse output per electrical cycle 01 = 2 pulses output per 3 electrical cycles 10 = 1 pulse output per 2 electrical cycles 11 = 1 pulse output per 3 electrical cycles 3:2 KtLckThr[1:0] Abnormal Kt lock detect threshold 00 = Kt_high = 3/2Kt. Kt_low = 3/4Kt 01 = Kt_high = 2Kt. Kt_low = 3/4Kt 10 = Kt_high = 3/2Kt. Kt_low = 1/2Kt 11 = Kt_high = 2Kt. Kt_low = 1/2Kt 1 SpdCtrlMd Speed input mode 0 = Analog input expected at SPEED pin 1 = PWM input expected at SPEED pin 0 CLoopDis 0 = Transfer to closed loop at Op2ClsThr speed 1 = No transfer to closed loop. Keep in open loop |
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