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DP83902AVLC 数据表(PDF) 40 Page - National Semiconductor (TI) |
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DP83902AVLC 数据表(HTML) 40 Page - National Semiconductor (TI) |
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40 / 70 page ![]() 120 Loopback Diagnostics (Continued) Since errored packets can be rejected the status associat- ed with these packets is lost unless the CPU can access the Receive Status Register before the next packer arrives In situations where another packet arrives very quickly the CPU may have no opportunity to do this The ST-NIC counts the number of packets with CRC errors and Frame Align- ment errors 8-Bit counters have been selected to reduce overhead The counters will generate interrupts whenever their MSBs are set so that a software routine can accumu- late the network statistics and reset the counter before overflow occurs The counters are sticky so that when they reach a count of 192 (C0H) counting is halted An additional counter is provided to count the number of packets the ST- NIC misses due to buffer overflow or being offline The structure of the counters is shown below Additional information required for network management is available in the Receive and Transmit Status Registers Transmit status is available after each transmission for infor- mation regarding events during transmission Typically the following statistics might be gathered in soft- ware Traffic Frames Sent OK Frames Received OK Multicast Frames Received Packets Lost Due to Lack of Resources RetriesPacket Errors CRC Errors Alignment Errors Excessive Collisions Packet with Length Errors Heartbeat Failure TLF11157 – 20 40 |
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