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AS7C256A 数据表(PDF) 4 Page - Alliance Semiconductor Corporation |
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AS7C256A 数据表(HTML) 4 Page - Alliance Semiconductor Corporation |
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4 / 9 page  ® AS7C256A 9/24/04; v.1.2 Alliance Semiconductor P. 4 of 9 Read cycle (over the operating range)2,8 Key to switching waveforms Read waveform 1 (address controlled)2,5,6,8 Read waveform 2 (CE controlled)2,5,7,8 Parameter Symbol -10 -12 -15 -20 Unit Notes Min Max Min Max Min Max Min Max Read cycle time tRC 10 –12–15– 20 – ns Address access time tAA – 10 – 12 – 15 – 20 ns 2 Chip enable (CE) access time tACE – 10 – 12 – 15 – 20 ns 2 Output enable (OE) access time tOE –5–6–7– 8 ns Output hold from address change tOH 3–3–3–3 – ns 4 CE LOW to output in low Z tCLZ 3–3–3–3 – ns 3,4 CE HIGH to output in high Z tCHZ –3–3–4– 5 ns 3,4 OE LOW to output in low Z tOLZ 0–0–0–0 – ns 3,4 OE HIGH to output in high Z tOHZ –3–3–4– 5 ns 3,4 Power up time tPU 0–0–0–0 – ns 3,4 Power down time tPD – 10 – 12 – 15 – 20 ns 3,4 Undefined output/don’t care Falling input Rising input Address Dout Data valid tOH tAA tRC Supply current CE OE Dout tRC1 tOE tOLZ tACE tCHZ tCLZ tPU tPD ICC ISB 50% 50% tOHZ Data valid |
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