DP8440VLJ-40 datasheet(43/46 Pages) NSC

部件名	DP8440VLJ-40

功能描述	microCMOS Programmable 16/64 Mbit Dynamic RAM Controller/Driver

PDF	46 Pages

Scroll/Zoom	100%

制造商	NSC [National Semiconductor (TI)]

网页	http://www.national.com

标志

43 / 46 page

130 Errata for DP844041 (Continued)

ERRATUM

When operating in Page Mode an access cannot start on

the clock edge immediately following the negation of

DTACK If back-to-back accesses are done in this way the

CAS signals will remain low during a refresh as shown in the

timing diagram

Recommended Fix

There should be at least one idle clock between the nega-

tion of DTACK and the start of a new access

Illegal Back-to-Back Accesses in Page Mode

TLF11718 – 45

ERRATUM

When starting a page access there is a hold time from the

rising edge of the clock when ADS cannot assert This hold

time (parameter 423 in the datasheet) is 4 ns and only ap-

plies when operating in Page Mode

Recommended Fix

ADS assertion should be delayed at least 4 ns from the

rising edge of the clock when in Page Mode operation

Parameter 423 ADS Hold Time before Assertion

TLF11718 – 46

DP8440VLJ-40 数据表(PDF) 43 Page - National Semiconductor (TI)