DP8441VLJ-40 datasheet(7/46 Pages) NSC

7 / 46 page

30 Signal Descriptions

31 ADDRESS AND CONTROL SIGNALS

Device (if not

Input

Description

Name

Applicable to All) Output

R0 – 11

DP8440

ROW ADDRESS

These inputs are used to specify the row address during an access to

the DRAM They are also used to program the chip when ML is asserted

R0 – 12

DP8441

C0 – 11

DP8440

COLUMN ADDRESS

These inputs are used to specify the column address during an

access to the DRAM They are also used to program the chip when ML is asserted

C0 – 12

DP8441

B0–B1

BANK SELECT

Depending on programming these inputs are used to select group RAS

and CAS outputs to assert during an access They are also used to program the chip when

the ML is asserted

ECAS0 – 3

DP8440

ENABLE CAS

These inputs asserted enable a single or group of CAS outputs In

combination with the B0 B1 and the programming selection these inputs select which

ECAS0 – 7

DP8441

CAS outputs will assert during an access The ECAS signals can also be used to toggle a

group of CAS outputs during page or burst mode accesses They are also used to program

the chip when ML is asserted

NoWRAP

NO WRAP

Asserting this signal causes the column address to be incremented

sequentially by one The column address will not wrap around if NoWRAP is asserted

(EXTNDRF)

When RFIP is asserted this signal is an EXTNDRF used to extend refresh by any number

of CLK periods until EXTNDRF is negated

NoLATCH

DP8441

COLUMN ADDRESS LATCH DISABLE

This input will disable ADS from latching the

column address when Latch Mode is selected

ADS

ADDRESS STROBE

This input starts every access Depending on programming this input

could latch the column address from the rising edge

CHIP SELECT

This input signal must be asserted to enable ADS to start an access

DTACK

DATA TRANSFER ACKNOWLEDGE

This output can be programmed to insert wait

states into a CPU access cycle DTACK negated signifies a wait condition when asserted

signifies that the access has taken place This signal can be delayed a number of positive

or negative edges of clock During burst accesses DTACK transitions increment the

column address

NADTACK

NEXT ADDRESS or EARLY DTACK

This output asserts one clock cycle before DTACK

This output can be used to request the next address in a sort of pipelining fashion or it

provides more time when DTACK needs to be generated externally

WAITIN

DP8441

WAIT INPUT

This input asserted delays DTACK for one extra clock period

GRANT

MEMORY ACCESS GRANT

The GRANT input functions as an output enable If negated

it forces the outputs to a TRI-STATE condition

PAGMISS

PAGE MISS

When programmed as an output this signal asserts when either the row or

the bank address changes from the previous access cycle or the column address has

been incremented beyond the page boundary If this pin is programmed as an input it is

the responsibility of the system to tell the controller if the next access is within the page

Useful for CPUs with internal page comparators PAGMISS is valid only if ADS and CS are

asserted

BSTARQ

BURST ACCESS REQUEST

This input enables the Burst Access Mode This input can be

programmed to be active high or active low

BSTARQ

DP8441VLJ-40 数据表(PDF) 7 Page - National Semiconductor (TI)

DP8441VLJ-40 数据表(HTML) 7 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

数据表下载

链接网址

DP8441VLJ-40 数据表(PDF) 7 Page - National Semiconductor (TI)

DP8441VLJ-40 数据表(HTML) 7 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

数据表 下载

链接网址

数据表下载