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TAS3208IPZPR 数据表(PDF) 33 Page - Texas Instruments

部件名 TAS3208IPZPR
功能描述  DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE
PDF  79 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TAS3208IPZPR 数据表(HTML) 33 Page - Texas Instruments

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TAS3208
www.ti.com
SLES201E
– JANUARY 2007 – REVISED MARCH 2011
I2C Slave Mode Operation
The I2C slave mode is the mode that is used to change configuration parameters during operation and perform
program and coefficient downloads from a master device. The latter can be used to replace the I2C master mode
EEPROM download.
The TAS3208 uses the slave mode to load the memory contents for the:
Microprogram memory
Micro extended memory
DSP program memory
DSP coefficient memory
DSP data memory
Update coefficient and other control values
Read status flags
The TAS3208 support both random and sequential I2C transactions. The TAS3208 I2C slave address is
011010X, where the first six bits are the TAS3208 device address and the final one bit is set by the TAS3208
internal microprocessor at power up. The internal microprocessor derives the last bit from an external pin
(CS),which is pulled up or down to create two unique addresses for control of multiple TAS3208 part
applications. The pulldown resistance of CS creates a default 00 address when no connection is made to the pin.
The TAS3208 I2C block does respond to the broadcast address (00h).
NOTE
When acting as an I2C slave, data-rate transfer is determined by the master device on the
bus. However, the setting of I2C parameter N at subaddress 0x01 does play a role in
setting the maximum possible data transfer rate. In the I2C slave mode, bit rates other
than (and including) the I2C-specific 100-Kbps and 400-Kbps bit rates can be obtained, but
N must always be set so that the oversample clock into the I2C master and slave
controllers is at least a factor of 20 higher in frequency than SCL.
N = 0 is a special case. When N = 0, a mode is enabled that detects I2C frames and enables the TAS3208 I2C
interface to reset and continue operation after receiving an invalid I2C frame.
Table 9.
I2C Slave Addresses
SLAVE ADDRESS
CS
0x68/69
0
0x6A/6B
1
Table 10.
I2C Master Addresses
SLAVE ADDRESS
CS
0xA0/A1
0
0xA2/A3
1
Copyright
© 2007–2011, Texas Instruments Incorporated
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