TAS3208IPZPR datasheet(39/79 Pages) TI1

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55-BIT INSTRUCTION

Ext

ALU First Stage

ALU Second Stage

Data Memory Load

Coefficient Memory Load

Memory Store

P1OP

53–49

P2OP

48–42

MOP1

AD1

41–37

36–27

MOP2

AD2

23–14

26–24

MOP3

AD3

9–0

13–10

TAS3208

www.ti.com

SLES201E

– JANUARY 2007 – REVISED MARCH 2011

The key features of the delay memory are:

•

17408

× 24 delay memory locations

•

24 separately addressable pointers

•

Programmable Start/Stop address on each pointer

•

Pointers capable of accessing 24-bit or 48-bit words

•

Single-port access (one pointer access per access cycle)

•

Access cycle

< four DSP clocks

•

Self clearing

– INIT pin used to clear all memory to zero

•

Fully synchronous

•

DP1

–DP15: 16 24-bit pointers

•

RP1

–RP8: Eight 48-bit (full precision) pointers

Since all of the pointers are contiguous, it is only necessary to write the address END point. For example, if DP1

is to be a three-sample delay, the register DP1 should be set to 0x003. If RP1 is to be a three-sample delay, the

–DP1 and RP8–RP1 registers must be set to

a minimum of a one sample delay (one or two words).

DP1 Start address is defined as 000x0.

DP2 Start address is equal to DP1 end address + 1.

RP1 Start address is equal to DP16 end address + 1.

RP8 Start address is equal to RP7 end address + 2.

Since the Start/Stop address for each pointer is programmable anywhere in the delay RAM's address space, the

delay for any one channel can be anywhere in the delay RAM. There is, however, no address space collision

avoidance logic to separate the pointers. The user (or micro) must take care to avoid overlapping the address

spacing of each pointer.

Pointer register address endpoint registers DP16

–DP1 and RP8–RP1 are typically written only during the

initialization (fast load) mode of the device. Writing to these registers while the TAS3208 DSP core is accessing

the pointers may cause the pointers to cross the address space of another pointer.

To write to the delay RAM, the TAS3208 DSP core controller must present the data to be written on the

PT_DATA bus (LSB always in bit zero of the bus), select the pointer to be accessed by driving the PT_SEL pins,

and assert the PT_WZ pin for a minimum of four clocks. The pointer will not increment until a write has been

performed and the PT_WZ pin has been deasserted.

To perform a read, the PT_OUT bus may be read four clocks after PT_SEL is driven.

DSP Instruction Word

TAS3208 has a 55-bit instruction word. Each instruction has five independent operations, which can load two

operands from data memory and coefficient memory, store the result into data or coefficient memory, and

perform two parallel arithmetic operations.

Figure 30. Instruction Word

The TAS3208 instruction set is a superset of the TAS3208 instruction set, extending the DSP processing

capabilities for improved efficiency of FIR operations, as well as extending the addressable memory space. The

Ext instruction bit (bit 54) has been added to extend the internal memory address space by one bit, increasing

the memory space from 1K to 2K words.

The superset instruction word maintains backward compatibility with the 54-bit instruction word of the TAS3208

device, since the 54-bit instruction word required dummy storage of two bits in the EEPROM.

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