TAS5716PAP datasheet(13/64 Pages) TI1

13 / 64 page

SERIAL AUDIO PORTS SLAVE MODE

TAS5716

www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009

over recommended operating conditions (unless otherwise noted)

TEST

PARAMETER

MIN

TYP

MAX

UNIT

CONDITIONS

fSCLKIN

Frequency, SCLK 32 × fS, 48 × fS, 64 × fS

CL = 30 pF

1.024

12.288

MHz

tsu1

Setup time, LRCLK to SCLK rising edge

th1

Hold time, LRCLK from SCLK rising edge

tsu2

Setup time, SDIN to SCLK rising edge

th2

Hold time, SDIN from SCLK rising edge

LRCLK frequency

192

kHz

SCLK duty cycle

40%

50%

60%

LRCLK duty cycle

40%

50%

60%

SCLK

SCLK rising edges between LRCLK rising edges

edges

t(edge)

SCLK

LRCLK clock edge with respect to the falling edge of SCLK

–1/4

1/4

period

Figure 1. Slave-Mode Serial-Data Interface Timing

Submit Documentation Feedback

Product Folder Link(s): TAS5716

TAS5716PAP 数据表(PDF) 13 Page - Texas Instruments

TAS5716PAP 数据表(HTML) 13 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

数据表下载