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DS20005206A-page 13

11AA02UID

4.5

Read Status Register (RDSR)

Instruction

The

register. The STATUS register may be read at any time,

even during a write cycle. The STATUS register is

formatted as follows:

The Write-In-Process (WIP) bit indicates whether the

11AA02UID is busy with a write operation. When set to

a ‘

is in progress. This bit is read-only.

The Write Enable Latch (WEL) bit indicates the status

of the write enable latch. When set to a ‘

allows writes to the array, when set to a ‘

prohibits writes to the array. This bit is set and cleared

using the WREN and WRDI instructions, respectively.

This bit is read-only for any other instruction.

The Block Protection (BP0 and BP1) bits indicate

which blocks are currently write-protected. These bits

are set by the user through the

These bits are nonvolatile.

The WIP and WEL bits will update dynamically (asyn-

chronous to issuing the

more, after the STATUS register data is received, the

master can provide a MAK during the Acknowledge

sequence to request that the data be transmitted again.

This allows the master to continuously monitor the WIP

and WEL bits without the need to issue another full

command.

Once the master is finished, it provides a NoMAK to

end the operation.

FIGURE 4-6:

READ STATUS REGISTER COMMAND SEQUENCE

7654

3

2

1

0

XXXX

BP1

BP0

WEL

WIP

Note: Bits 4-7 are don’t cares, and will read as ‘

Note:

If Read Status Register command is

initiated while the 11AA02UID is currently

executing an internal write cycle on the

STATUS

register,

the

new

Block

Protection bit values will be read during

the entire command.

Note:

The current drawn for a Read Status

Register command during a write cycle is

Write operating currents.

11

0

1

0

1

00

Start Header

SCIO

Device Address

00

0

0

1

0

10

Command

11

0

0

0

0

00

Standby Pulse

SCIO

STATUS Register Data

32 1 0

The STATUS register data can continuously be read, or polled, by transmitting a MAK in place of the NoMAK.

Note:

0

0

0

0