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TFP401, TFP401A

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SLDS120G – MARCH 2000 – REVISED MAY 2016

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11 Power Supply Recommendations

Use solid ground planes and tie ground planes together with as many vias as is practical. This will provide a

desirable return path for current. Each supply should be on separate split power planes, where each power plane

should be as large an area as possible. Connect PanelBus receiver power and ground pins and all bypass caps

to appropriate power or ground plane with via. Vias should be as fat and short as practical, the goal is to

minimize the inductance.

•

DVDD: Place one 0.01 uF capacitor as close as possible between each DVDD device pin (Pins 6, 38, 67)

and ground. A 22 uF tantalum capacitor should be placed between the supply and 0.01 uF capacitors. A

ferrite bead should be used between the source and the 22 uF capacitor.

•

OVDD: Place one 0.01 uF capacitor as close as possible between each OVDD device pin (Pins 18, 29, 43,

57, 78) and ground. A 22 uF tantalum capacitor should be placed between the supply and 0.01 uF capacitors.

A ferrite bead should be used between the source and the 22 uF capacitor.

•

AVDD: Place one 0.01 uF capacitor as close as possible between each AVDD device pin (Pins 82, 84, 88,

95) and ground. A 22 uF tantalum capacitor should be placed between the supply and 0.01 uF capacitors. A

ferrite bead should be used between the source and the 22 uF capacitor.

•

PVCC: Place three 0.01 uF capacitors in parallel as close as possible between the PVDD device pin (Pin 97)

and ground. A 22 uF tantalum capacitor should be placed between the supply and 0.01 uF capacitors. A

ferrite bead should be used between the source and the 22 uF capacitor.

12 Layout

12.1 Layout Guidelines

12.1.1 Layer Stack

The pinout of Texas Instruments High Speed Interface (HSI) devices features differential signal pairs and the

an example, consider a device X which is a repeater/re-driver, so both its inputs and outputs are high-speed

differential signals. These guidelines can be applied to other high-speed devices such as drivers, receivers,

multiplexers, etc. A minimum of four layers is required to accomplish a low EMI PCB design. Layer stacking

should be in the following order (top-to-bottom): high-speed differential signal layer, ground plane, power plane

and control signal layer.

Figure 24. Layer Stack