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TFP401, TFP401A

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SLDS120G – MARCH 2000 – REVISED MAY 2016

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Copyright © 2000–2016, Texas Instruments Incorporated

(1)

Some TMDS transmitters transmit a CTL0 signal. The TFP401/401A decodes and transfers CTL[3:1]

and ignores CTL0 characters. CTL0 is not available as a TFP401/401A output.

Table 1. TMDS Pixel Data and Control Signal Encoding

RECEIVED PIXEL DATA

ACTIVE DISPLAY DE = HIGH

INPUT CHANNEL

OUTPUT PINS

(VALID FOR DE = HIGH)

Red[7:0]

Channel-2 (Rx2 ±)

QE[23:16] QO[23:16]

Green[7:0]

Channel-1 (Rx1 ±)

QE[15:8] QO[15:8]

Blue[7:0]

Channel-0 (Rx0 ±)

QE[7:0] QO[7:0]

RECEIVED CONTROL DATA

BLANKING DE = LOW

INPUT CHANNEL

OUTPUT PINS

(VALID FOR DE = LOW)

CTL[3:2]

Channel-2 (Rx2 ±)

CTL[3:2]

Channel-1 (Rx1 ±)

CTL1

HSYNC, VSYNC

Channel-0 (Rx0 ±)

HSYNC, VSYNC

The TFP401/401A discriminates between valid pixel TMDS characters and control TMDS characters to

determine the state of active display versus blanking, i.e., the state of DE.

9.3.2 TFP401/401A Clocking and Data Synchronization

The TFP401/401A receives a clock reference from the DVI transmitter that has a period equal to the pixel time,

contains 10 bits per 8-bit pixel, it follows that the Rx[2:0] serial bit rate is 10 times the pixel rate. For example, the

required pixel rate to support a UXGA resolution with 60-Hz refresh rate is 165 MHz. The TMDS serial bit rate is

10× the pixel rate, or 1.65 Gb/s. Due to the transmission of this high-speed digital bit stream, on three separate

channels (or twisted-pair wires) of long distances (3–5 meters), phase synchronization between the data steams

and the input reference clock is not assured. In addition, skew between the three data channels is common. The

TFP401/401A uses a 4× oversampling scheme of the input data streams to achieve reliable synchronization with

and external noise sources is also typical of high-speed serial data transmission; hence, the TFP401/401A

design for high jitter tolerance.

The input clock to the TFP401/401A is conditioned by a phase-locked loop (PLL) to remove high-frequency jitter

from the clock. The PLL provides four 10× clock outputs of different phase to locate and sync the TMDS data

streams (4× oversampling). During active display, the pixel data is encoded to be transition-minimized, whereas

in blank, the control data is encoded to be transition-maximized. A DVI-compliant transmitter is required to

the receiver sees a transition-maximized code. Synchronization during blank, when the data is transition-

maximized, ensures reliable data-bit boundary detection. Phase synchronization to the data streams is unique for

each of the three input channels and is maintained as long as the link remains active.

9.3.3 TFP401/401A TMDS Input Levels and Input Impedance Matching

TFP401/401A is internally optimized using a laser trim process to precisely fix the impedance at 50

Ω. The

device functions normally with or without a resistor on the EXT_RES pin, so it remains drop-in compatible with

current sockets. The fixed impedance eliminates the need for an external resistor while providing optimum

impedance matching to standard 50-

Ω DVI cables.

Figure 15 shows a conceptual schematic of a DVI transmitter and TFP401/401A receiver connection. A

transmitter drives the twisted-pair cable via a current source, usually achieved with an open-drain type output

driver. The internal resistor, which is matched to the cable impedance at the TFP401/401A input, provides a

differential signal is shown in Figure 16. The TFP401/401A is designed to respond to differential signal swings