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CY2210
Document #: 38-07204 Rev. *A
Page 5 of 10
Switching Characteristics[4, 5] Over the Operating Range
Parameter
Output
Description
Test Conditions
Min.
Max.
Unit
t1
All
Output Duty Cycle[6]
t1A/t1B
45
55
%
t2
CPU, CPU/2,
APIC
Rising Edge Rate
Between 0.4V and 2.0V
1.0
4.0
V/ns
t2
USB, REF
Rising Edge Rate
Between 0.4V and 2.4V
0.5
2.0
V/ns
t2
PCI, AGP
Rising Edge Rate
Between 0.4V and 2.4V
1.0
4.0
V/ns
t3
CPU, CPU/2,
APIC
Falling Edge Rate
Between 2.0V and 0.4V
1.0
4.0
V/ns
t3
USB, REF
Falling Edge Rate
Between 2.4V and 0.4V
0.5
2.0
V/ns
t3
PCI, AGP
Falling Edge Rate
Between 2.4V and 0.4V
1.0
4.0
V/ns
t6
CPU
CPU-CPU Skew
Measured at 1.25V
175
ps
t7
CPU/2
CPU/2-CPU/2 Skew
Measured at 1.25V
175
ps
t8
APIC
APIC-APIC Skew
Measured at 1.25V
250
ps
t9
AGP
AGP-AGP Skew
Measured at 1.5V
250
ps
t10
PCI
PCI-PCI Skew
Measured at 1.5V
500
ps
t11
CPU, AGP
CPU-AGP Clock Skew
CPU leads. Measured at 1.25V for
2.5V clocks and 1.5V for 3.3V clocks
0
1.5
ns
t12
AGP, PCI
AGP-PCI Clock Skew
AGP leads. Measured at 1.5V
1.5
4.0
ns
t13
CPU, APIC
CPU-APIC Clock Skew
CPU leads. Measured at 1.25V
1.5
4
ns
t14
CPU, PCI
CPU-PCI Clock Skew
CPU leads. Measured at 1.25V clocks
and 1.5V for 3.3V clocks
1.5
4
ns
CPU
Cycle-Cycle Clock Jitter
With all outputs running (CY2210-2)
150
ps
CPU
Cycle-Cycle Clock Jitter
With all outputs running
(CY2210-3/-4)
250
ps
CPU
Cycle-Cycle Clock Jitter
With the USB output turned off
(CY2210-3/-4)
200
ps
CPU/2
Cycle-Cycle Clock Jitter
250
ps
APIC
Cycle-Cycle Clock Jitter
500
ps
USB
Cycle-Cycle Clock Jitter
500
ps
AGP
Cycle-Cycle Clock Jitter
500
ps
REF
Cycle-Cycle Clock Jitter
1000
ps
CPU, PCI
Settle Time
CPU and PCI clock stabilization from
power-up
3
ms
Notes:
5.
All parameters specified with loaded outputs.
6.
Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V.
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