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TLV2465CPWR 数据表(PDF) 29 Page - Texas Instruments |
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TLV2465CPWR 数据表(HTML) 29 Page - Texas Instruments |
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29 / 71 page ![]() TLV2460, TLV2461, TLV2462, TLV2463, TLV2464, TLV2465, TLV246xA FAMILY OF LOW POWER RAILTORAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 29 WWW.TI.COM APPLICATION INFORMATION macromodel information Macromodel information provided was derived using Microsim Parts Release 8, the model generation software used with Microsim PSpice . The Boyle macromodel (see Note 2) and subcircuit in Figure 54 are generated using the TLV246x typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): D Maximum positive output voltage swing D Maximum negative output voltage swing D Slew rate D Quiescent power dissipation D Input bias current D Open-loop voltage amplification D Unity-gain frequency D Common-mode rejection ratio D Phase margin D DC output resistance D AC output resistance D Short-circuit output current limit NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Intergrated Circuit Operational Amplifiers”, IEEE Journal of Solid-State Circuits, SC-9, 353 (1974). + − + − + − + − + − .SUBCKT TLV246X 1 2 3 4 5 C1 11 12 2.46034E−12 C2 6 7 10.0000E−12 CSS 10 99 443.21E−15 DC 5 53 DY DE 54 5 DY DLP 90 91 DX DLN 92 90 DX DP 43DX EGND 99 0 POLY (2) (3,0) (4,0) 0 .5 .5 FB 7 99 POLY (5) VB VC VE VLP + VLN 0 21.600E6 −1E3 1E3 22E6 −22E6 GA 6 0 11 12 345.26E−6 GCM 0 6 10 99 15.4226E−9 ISS 10 4 DC 18.850E−6 HLIM 90 0 VLIM 1K J1 11 2 10 JX1 J2 12 1 10 JX2 R2 6 9 100.00E3 RD1 3 11 2.8964E3 RD2 3 12 2.8964E3 R01 8 5 5.6000 R02 7 99 6.2000 RP 3 4 8.9127 RSS 10 99 10.610E6 VB 9 0 DC 0 VC 3 53 DC .7836 VE 54 4 DC .7436 VLIM 7 8 DC 0 VLP 91 0 DC 117 VLN 0 92 DC 117 .MODEL DX D (IS=800.00E−18) .MODEL DY D (IS=800.00E−18 Rs = 1m Cjo=10p) .MODEL JX1 NJF (IS=1.0000E−12 BETA=6.3239E−3 + VTO= −1) .MODEL JX2 NJF (IS=1.0000E−12 BETA=6.3239E−3 + VTO= −1) .ENDS VDD + RP IN − 2 IN + 1 GND RD1 11 J1 J2 10 RSS ISS 3 12 RD2 DP VD DC 4 C1 53 EGND FB HLIM 90 DLP 91 DLN 92 VLN VLP 99 CSS + − VE DE 54 OUT + − + − R2 6 9 VB C2 GA VLIM 8 5 RO1 RO2 7 GCM Figure 54. Boyle Macromodels and Subcircuit PSpice and Parts are trademarks of MicroSim Corporation. Device TLV2465A is Obsolete |
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