TNETV2685FIBZUT11 datasheet(107/190 Pages) TI1

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TMS320DM647

TMS320DM648

www.ti.com

SPRS372H – MAY 2007 – REVISED APRIL 2012

Table 6-34. High-Speed Bypass Capacitors (continued)

NO.

PARAMETER

MIN

MAX

UNIT

DDR#1 HS Bypass Capacitor Count(3)

Devices

DDR#1 HS Bypass Capacitor Total Capacitance

0.4

μF

DDR#2 HS Bypass Capacitor Count(3) (4)

Devices

DDR#2 HS Bypass Capacitor Total Capacitance(4)

0.4

μF

(4)

Only used on 32-bit wide DDR2 memory systems

Table 6-35. Clock Net Class Definitions

CLOCK NET CLASS

DSP PIN NAMES

DDR_CLK/DDR_CLK

DQS0

DDR_DQS0/DDR_DQS0

DQS1

DDR_DQS1/DDR_DQS1

DQS2(1)

DDR_DQS2/DDR_DQS2

DQS3(1)

DDR_DQS3/DDR_DQS3

(1)

Only used on 32-bit wide DDR2 memory systems.

Table 6-36. Signal Net Class Definitions

CLOCK NET CLASS

ASSOCIATED CLOCK NET CLASS

DSP PIN NAMES

ADDR_CTRL

DDR_BA[2:0], DDR_A[13:0], DDR_CS, DDR_CAS, DDR_RAS,

DDR_WE, DDR_CKE

DQ0

DQS0

DDR_D[7:0], DDR_DQM0

DQ1

DQS1

DDR_D[15:8], DDR_DQM1

DQ2(1)

DQS2

DDR_D[23:16], DDR_DQM2

DQ3(1)

DQS3

DDR_D[31:24], DDR_DQM3

DQGATEL

CK, DQS0, DQS1

DDR_DQGATE0, DDR_DQGATE1

DQGATEH(1)

CK, DQS2, DQS3

DDR_DQGATE2, DDR_DQGATE3

(1)

Only used on 32-bit wide DDR2 memory systems.

6.9.3.9

DDR2 Signal Termination

No terminations of any kind are required in order to meet signal integrity and overshoot requirements.

Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only

type permitted. Table 6-37 shows the specifications for the series terminators.

Table 6-37. DDR2 Signal Terminations

NO.

PARAMETER

MIN

TYP

MAX

UNIT

CK Net Class(1)

Ω

ADDR_CTRL Net Class(1) (2) (3)

Ω

Data Byte Net Classes (DQS0-DQS3, DQ0-DQ3)(1) (2) (3) (4)

Ω

DQGATE Net Classes (DQGATEL, DQGATEH)(1) (2) (3)

Ω

(1)

Only series termination is permitted, parallel or SST specifically disallowed.

(2)

Terminator values larger than typical only recommended to address EMI issues.

(3)

Termination value should be uniform across net class.

(4)

When no termination is used on data lines (0

Ωs), the DDR2 devices must be programmed to operate in 60% strength mode.

Peripheral Information and Electrical Specifications

107

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