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TNETV2685FIBZUT11 数据表(PDF) 109 Page - Texas Instruments |
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TNETV2685FIBZUT11 数据表(HTML) 109 Page - Texas Instruments |
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109 / 190 page  A1 A1 E0 T E1 T E2 DM648 E3 T T TMS320DM647 TMS320DM648 www.ti.com SPRS372H – MAY 2007 – REVISED APRIL 2012 Table 6-38. CK and ADDR_CTRL Routing Specification(1) NO PARAMETER MIN TYP MAX UNIT 1 Center to center CK-CK spacing 2w 2 CK A to B/A to C Skew Length Mismatch(1) 25 Mils 3 CK B to C Skew Length Mismatch 25 Mils 4 Center to center CK to other DDR2 trace spacing(2) 4w 5 CK/ADDR_CTRL nominal trace length(3) CACLM-50 CACLM CACLM+50 Mils 6 ADDR_CTRL to CK Skew Length Mismatch 100 Mils 7 ADDR_CTRL to ADDR_CTRL Skew Length Mismatch 100 Mils 8 Center to center ADDR_CTRL to other DDR2 trace spacing(2) 4w 9 Center to center ADDR_CTRL to other ADDR_CTRL trace spacing(2) 3w 10 ADDR_CTRL A to B/A to C Skew Length Mismatch(1) 100 Mils 11 ADDR_CTRL B to C Skew Length Mismatch 100 Mils (1) Series terminator, if used, should be located closest to DSP. (2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion. (3) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes. Figure 6-17 shows the topology and routing for the DQS and DQ net classes; the routes are point to point. Skew matching across bytes is not needed nor recommended. A. DM648 is shown in this figure as an example of the device and represents the entire set of devices that include: DM647/DM648. Figure 6-17. DQS and DQ Routing and Toplogy Table 6-39. DQS and DQ Routing Specification (1) NO. PARAMETER MIN TYP MAX UNIT 1 Center to center DQS-DQS spacing 2 w 2 DQS E Skew Length Mismatch 25 Mils 3 Center to center DQS to other DDR2 trace spacing(2) 4 w 4 DQS/DQ nominal trace length(1) (3) (4) (5) DQLM-50 DQLM DQLM+50 Mils 5 DQ to DQS Skew Length Mismatch(3) (4) (5) 100 Mils 6 DQ to DQ Skew Length Mismatch(3) (4) (5) 100 Mils (1) Series terminator, if used, should be located closest to DDR. (2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion. (3) A 16-bit DDR memory system has two sets of data net classes, one for data byte 0, and one for data byte 1, each with an associated DQS (2 DQSs). (4) A 32-bit DDR memory system will have four sets of data net classes, one each for data bytes 0 through 3, and each associated with a DQS (4 DQSs). (5) There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte 1. Copyright © 2007–2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 109 Submit Documentation Feedback Product Folder Link(s): TMS320DM647 TMS320DM648 |
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