CS5212

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5

PACKAGE PIN DESCRIPTION

PIN NO.

PIN SYMBOL

FUNCTION

1

GATE(H)

High Side Switch FET driver pin. Capable of delivering peak currents of 1.0 A.

2

BST

Power supply input for the high side driver.

3

LGND

Reference ground. All control circuits are referenced to this pin. IC substrate connection.

4

Input for the PWM comparator.

5

Error amplifier input.

6

COMP

Error Amp output. PWM Comparator reference input. A capacitor to LGND provides error amp

compensation.

7

SGND

Internal reference is connected to this ground. Connect directly at the load for ground remote

sensing.

8

A resistor from this pin to SGND sets switching frequency.

9

Input Power Supply Pin. It supplies power to control circuitry. A 0.1

µF Decoupling cap is

recommended.

10

IS–

Negative input for overcurrent comparator.

11

IS+

Positive input for overcurrent comparator.

12

Power supply input for the low side driver.

13

GATE(L)

Low Side Synchronous FET driver pin. Capable of delivering peak currents of 1.0 A.

14

PGND

High Current ground for the GATE(H) and GATE(L) pins.

UVLO

Comparator

5.0

µA

GATE(L)

GATE(H)

−

+

−

+

−

+

Σ

PGND

BST

R

S

Q

Q

S

R

Q

Q

Fault

Fault

PWM FF

COMP Discharge COMP

0.25 V

PWM Comparator

ART Ramp

OSC

0.5 V

Error Amp

1.0 V

100 % DC

Comparator

OC

Comparator

60 mV

0.8 V

UVLO

LGND

IS–

IS+

SGND

COMP

Figure 2. Block Diagram

Reset Dominant

Set Dominant