A29010B datasheet(8/30 Pages) AMICC

8 / 30 page

A29010B Series

PRELIMINARY

(June, 2016, Version 0.0)

AMIC Technology, Corp.

Sector Protection/Unprotection

The hardware sector protection feature disables both program

and erase operations in any sector. The hardware sector

unprotection feature re-enables both program and erase

operations in previously protected sectors.

Sector protection/unprotection must be implemented using

programming equipment. The procedure requires a high

voltage (VID) on address pin A9 and the control pins.

The device is shipped with all sectors unprotected.

It is possible to determine whether a sector is protected or

unprotected. See "Autoselect Mode" for details.

Hardware Data Protection

The

requirement

command

unlocking

sequence

for

programming or erasing provides data protection against

inadvertent writes (refer to the Command Definitions table). In

addition, the following hardware data protection measures

prevent accidental erasure or programming, which might

otherwise be caused by spurious system level signals during

VCC power-up transitions, or from system noise. The device is

powered up to read array data to avoid accidentally writing

data to the array.

Write Pulse "Glitch" Protection

Noise pulses of less than 5ns (typical) on

OE , CE or WE

do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of

OE =VIL, CE

= VIH or

WE = VIH. To initiate a write cycle, CE and WE

must be a logical zero while

OE is a logical one.

Power-Up Write Inhibit

WE = CE = VIL and OE = VIH during power up, the device

does not accept commands on the rising edge of

WE . The

internal state machine is automatically reset to reading array

data on the initial power-up.

Command Definitions

Writing specific address and data commands or sequences

into the command register initiates device operations. The

Command

Definitions

table

defines

the

valid

command sequences. Writing incorrect address and data

values or writing them in the improper sequence resets the

device to reading array data.

All addresses are latched on the falling edge of

WE or CE ,

whichever happens later. All data is latched on the rising edge

WE or CE , whichever happens first. Refer to the

appropriate timing diagrams in the "AC Characteristics"

section.

Reading Array Data

The device is automatically set to reading array data after

device power-up. No commands are required to retrieve data.

The device is also ready to read array data after completing

an Embedded Program or Embedded Erase algorithm. After

the device accepts an Erase Suspend command, the device

enters the Erase Suspend mode. The system can read array

data using the standard read timings, except that if it reads at

an address within erase-suspended sectors, the device

outputs status data.

After completing a programming operation in the Erase

Suspend mode, the system may once again read array data

with the same exception. See "Erase Suspend/Erase Resume

Commands" for more information on this mode.

The system must issue the reset command to re-enable the

device for reading array data if I/O5 goes high, or while in the

autoselect mode. See the "Reset Command" section, next.

See also "Requirements for Reading Array Data" in the

"Device Bus Operations" section for more information. The

Read Operations table provides the read parameters, and

Read Operation Timings diagram shows the timing diagram.

Reset Command

Writing the reset command to the device resets the device to

reading array data. Address bits are don't care for this

command. The reset command may be written between the

sequence cycles in an erase command sequence before

erasing begins. This resets the device to reading array data.

Once erasure begins, however, the device ignores reset

commands until the operation is complete.

The reset command may be written between the sequence

cycles in a program command sequence before programming

begins. This resets the device to reading array data (also

applies to programming in Erase Suspend mode). Once

programming begins, however, the device ignores reset

commands until the operation is complete.

The reset command may be written between the sequence

cycles in an autoselect command sequence. Once in the

autoselect mode, the reset command must be written to return

to reading array data (also applies to autoselect during Erase

Suspend).

If I/O5 goes high during a program or erase operation, writing

the reset command returns the device to reading array data

(also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system to

access the manufacturer and devices codes, and determine

whether or not a sector is protected. The Command

Definitions table shows the address and data requirements.

This method is an alternative to that shown in the Autoselect

Codes (High Voltage Method) table, which is intended for

PROM programmers and requires VID on address bit A9.

The autoselect command sequence is initiated by writing two

unlock cycles, followed by the autoselect command. The

device then enters the autoselect mode, and the system may

read at any address any number of times, without initiating

another command sequence.

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The program

command sequence is initiated by writing two unlock write

cycles, followed by the program set-up command. The

program address and data are written next, which in turn

initiate the Embedded Program algorithm. The system is not

required to provide further controls or timings. The device

automatically provides internally generated program pulses

and verify the programmed cell margin. The Command

Definitions table shows the address and data requirements for

the byte program command sequence.

When the Embedded Program algorithm is complete, the

device then returns to reading array data and addresses are

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