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A29010B 数据表(PDF) 23 Page - AMIC Technology |
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A29010B 数据表(HTML) 23 Page - AMIC Technology |
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23 / 30 page ![]() A29010B Series PRELIMINARY (June, 2016, Version 0.0) 22 AMIC Technology, Corp. Timing Waveforms for Alternate CE Controlled Write Operation Erase and Programming Performance Parameter Typ. (Note 1) Max. (Note 2) Unit Comments Sector Erase Time 0.3 1.5 sec Chip Erase Time 1 4 sec Excludes 00h programming prior to erasure (Note 4) Byte Programming Time 6 100 μs Chip Programming Time (Note 3) 1 4 sec Excludes system-level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 5.0V VCC, 10,000 cycles. Additionally, programming typically assumes checkerboard pattern. 2. Under worst case conditions of 90 °C, VCC = 4.5V (4.75V for -55), 100,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does the device set I/O5 = 1. See the section on I/O5 for further information. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 4 for further information on command definitions. 6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles. Addresses WE OE CE Data 555 for program 2AA for erase PA DOUT I/O7 Data Polling Note : 1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O7 = Complement of Data Input, DOUT = Array Data. 2. Figure indicates the last two bus cycles of the command sequence. PD for program 30 for sector erase 10 for chip erase tBUSY tWHWH1 or 2 tAH tAS tWC tWH tGHEL tCP tWS tCPH PA for program SA for sector erase 555 for chip erase A0 for program 55 for erase tRH tDS tDH |
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