TNETE2004

MDIO-MANAGED QuadPHY

FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

1

POST OFFICE BOX 655303

– Four 10BASE-T Physical-Layer (PHY)

Interfaces in One Package Minimizing

PCB Footprint for Internetworking

Applications

Compliant

– Full-Duplex: Independent Transmit and

Receive Channels for Operation at

20-Mbit/s Aggregate

Specification

Serial Compliant With IEEE Std 802.3

Media-Independent Interface (MII)

Transmit Circuits

– No External Filters Are Required

– Meets IEEE Std 802.3 (Section 14.3)

Electrical Requirements

Auto-Negotiation to Establish the Highest

Common Protocol

(PLL)

Channels

Indicators

LED Status Indicators

Consumption

(TAP)

Is User Programmable

Quad Flat Package (PBE) and 128-Pin

Plastic Quad Flat Package (PAC)

description

The TNETE2004 QuadPHY interface device is a single-chip, multi-PHY (four 10BASE-T devices),

high-performance solution for designers of 10BASE-T networking systems. The highly integrated TNETE2004

includes a user-programmable SNI signal for each PHY. Each PHY interface on the device provides Manchester

encoding/decoding of data via unshielded twisted-pair (UTP) balanced cable through simple isolation

transformers requiring no external filtering. Additional TNETE2004 features are smart squelch, jabber

detection, auto-polarity correction, transmission wave shaping, and anti-alias filtering capabilities. Each PHY

interface on the TNETE2004 is individually addressable within the TNETE2004 via the MDIO.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright

© 1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

† IEEE Std 1149.1-1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture