Connection Diagrams

Pin Descriptions

TSI

Transmit PCM serial data input. TSI is an 8-bit PCM data

stream and is shifted into an 8-bit serial-to-parallel register

on the falling edges of PSCK while CE and TRB are high.

The last 8 bits of TSI are latched and transferred to the core

for processing at the falling edge of CE.

TSO

data bit stream of 4- to 5-bit length, and is shifted out with the

rising edge of ASCK when CE is high following the process-

ing of a transmit channel. TSO is in TRI-STATE mode while

CE is low or while RSO output is active.

RSI

Receive ADPCM serial data input. RSI is a data bit stream of

4- to 5-bit length, and is shifted in with the falling edges of

ASCK while CE is high and TRB is low. The last 4 or 5 bits of

RSI are latched and transferred to the core for processing at

the falling edge of CE.

RSO

Receive PCM TRI-STATE serial data output. RSO is an 8-bit

PCM data stream and is shifted out with the rising edges of

PSCK when CE is high following the processing of a receive

channel. RSO is in TRI-STATE mode while CE is low or while

TSO output is active.

PSCK

PCM serial clock input. PSCK is used to shift PCM data into

TSI or out of RSO while CE is active (high). The transfer de-

pends on the logic state of TRB.

ASCK

ADPCM serial clock input. ASCK is used to shift ADPCM

data into RSI or out of TSO while CE is active (high). The

transfer depends on the logic state of TRB.

CLK

Master clock input. CLK may be asynchronous to PSCK or

ASCK.

CE

Chip enable input. When CE is high, it enables data transfer.

The falling edge of CE latches and transfers the serial data

TSI or RSI to the core for processing and strobes the control

signals QSEL0, QSEL1, PCM1, EN and INIT. CE should

change state only when PSCK and ASCK are high. CE,

when low, sets the TSO and RSO outputs into TRI-STATE

mode.

TRB

Transmitter or receiver select. A logic low at TRB selects the

receiver of the channel processed. A logic high enables the

transmitter of the channel processed. TRB determines which

input register is enabled and which output register and out-

put is enabled. TRB should be stable while CE is high.

EN

Channel enable input. EN is strobed in with the falling edge

of CE. A logic high at the falling edge of CE indicates that the

channel is active, and the ADPCM will process the data just

clocked in.

INIT

Channel initialization input. INIT is read at the falling edge of

CE. A logic high at the falling edge of CE causes the ADPCM

processor to initialize the channel currently processing.

PCM1

PCM coding law select. A logic low at PCM1 selects 8-bit

µ-law, while a logic high selects 8-bit A-law with even bit in-

version.

Plastic Chip Carrier

DS012902-2

Top View

Order Number TP11368V

See NS Package Number V28A

Plastic Dual-In-Line

DS012902-3

Top View

Order Number TP11368N

See NS Package Number N24A

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