Table 3 shows the position of the ADPCM data in the 5-bit in-

put register when five ASCK low going pulses are available

while CE is high. Only the last four bits of the ADPCM input

register prior to the falling edge of CE are latched in and

transferred to the core for processing in the 32, 24 and 16

kbps modes. In the 40 kbps mode, the last five bits prior to

7

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