SN0402002DBVR datasheet(7/31 Pages) TI1

7 / 31 page

IT-

0.4 V

Output Condition

Undefined

Output Condition

Undefined

RESET

TPS3103, TPS3106, TPS3110

www.ti.com

SLVS363F – AUGUST 2001 – REVISED NOVEMBER 2015

7.6 Timing Requirements

At RL = 1 MΩ, CL = 50 pF, and TA = –40°C to 85°C, unless otherwise noted.

MIN

TYP

MAX

UNIT

tT(OUT)

Time-out period

at WDI

VDD ≥ 0.85 V

0.55

1.1

1.65

at VDD

VIH = 1.1 × VIT–, VIL = 0.9 × VIT–, VIT– = 0.86 V

at MR

VDD ≥ VIT– + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD

0.1

Pulse width

at SENSE

VDD ≥ VIT–, VIH = 1.1 × VIT − (S), VIL = 0.9 × VIT − (S)

μs

at PFI

VDD ≥ 0.85 V, VIH = 1.1 × VIT − (S),VIL = 0.9 × VIT − (S)

at WDI

VDD ≥ VIT–, VIL = 0.3 × VDD, VIH = 0.7 × VDD

0.3

7.7 Switching Characteristics

At RL = 1 MΩ, CL = 50 pF, and TA = –40°C to 85°C, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VDD ≥ 1.1 × VIT–, MR = 0.7 × VDD.

Delay time

130

195

See Timing Requirements.

Propagation delay time,

VDD to RESET or

tPHL(VDD)

VIH = 1.1 × VIT–, VIL = 0.9 × VIT–

μs

high-to-low level output

RSTVDD delay

Propagation delay time,

SENSE to RESET or

tPHL(SENSE)

VDD ≥ 0.8 V, VIH = 1.1 × VIT–, VIL = 0.9 × VIT–

μs

high-to-low level output

RSTSENSE delay

Propagation delay time,

tPHL(PFO)

PFI to PFO delay

VDD ≥ 0.8 V, VIH = 1.1 × VIT–, VIL = 0.9 × VIT–

μs

high-to-low level output

Propagation delay time,

tPLH(PFO)

PFI to PFO delay

VDD ≥ 0.8 V, VIH = 1.1 × VIT–, VIL = 0.9 × VIT–

300

μs

low-to-high level output

MR to RESET.

Propagation delay time,

tPHL(MR)

RSTVDD,

VDD ≥ 1.1 × VIT–, VIL = 0.3 × VDD, VIH = 0.7 × VDD

μs

high-to-low level output

RSTSENSE delay

Figure 1. RESET Timing Diagram for TPS3103

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