SN0402002DBVR datasheet(12/31 Pages) TI1

12 / 31 page

Reset Logic

and Timer

0.551 V

PFI

GND

RESET

PFO

TPS3103

TPS3103, TPS3106, TPS3110

SLVS363F – AUGUST 2001 – REVISED NOVEMBER 2015

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8 Detailed Description

8.1 Overview

The TPS310x and TPS311x families of supervisory circuits operate from supply voltages from 0.9 V to 3.3 V and

provide circuit initialization and timing supervision for DSP- and processor-based systems. During power-on,

RESET is asserted when the supply voltage (VDD) exceeds 0.4 V. The devices monitor VDD and keep the RESET

output low as long as VDD remains below the threshold voltage (VIT–). To ensure proper system reset, after VDD

surpasses the threshold voltage plus the hysteresis (VIT– + VHYS) an internal timer delays the transition of the

RESET signal from low to high for the specified time. The delay time starts after VDD has risen above (VIT– +

VHYS). When VDD drops below VIT–, the output becomes active again.

All the devices of this family have a fixed-VDD threshold voltage (VIT–) set by an internal voltage divider. The

TPS3103 and TPS3106 devices both have an active-low, open-drain RESET output. The TPS3103 device has

an integrated power-fail input (PFI) and corresponding power-fail output (PFO) that can be used for low-battery

detection or for monitoring a power supply other than the input supply. The TPS3106 device has a SENSE input

with a corresponding output (RSTSENSE) for monitoring voltages other than the input supply. The TPS3110

device has an active-low push/pull RESET and a watchdog timer that is used for monitoring the operation of

microprocessors. All three devices have manual reset pin (MR) that can be used to force the outputs low

regardless of the sensed voltages.

8.2 Functional Block Diagrams

Figure 12. TPS3103 Functional Block Diagram

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Product Folder Links: TPS3103 TPS3106 TPS3110

SN0402002DBVR 数据表(PDF) 12 Page - Texas Instruments