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VT8231 数据表(PDF) 71 Page - List of Unclassifed Manufacturers

部件名 VT8231
功能描述  SOUTH BRIDGE PC99 COMPLIANT
PDF  132 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
网页  
标志 ETC - List of Unclassifed Manufacturers

VT8231 数据表(HTML) 71 Page - List of Unclassifed Manufacturers

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VT8231
Preliminary Revision 0.8 October 29, 1999
-65-
Function 0 Registers - PCI to ISA Bridge
7HFKQRORJLHV ,QF
:H &RQQHFW
:H &RQQHFW
Offset 76 – GPIO Control 3..............................................RW
7
Over-Current (OC) Input
0
Disable ...................................................default
1Enable
6
OC[3:0] From SD[3:0] By Scan
0
Disable ...................................................default
1Enable
5
GPO14 / GPO15 Enable (Pins E12 / D12)
0
Pins used for IRTX and IRRX ...............default
1
Pins used for GPO14 and GPO15
4
MCCS# Pin Select
0
MCCS# is on Pin U5 ..............................default
1
MCCS# is on Pin U8
3
MCCS# Function
0
Disable MCCS# function on U5/U8.......default
1
Enable MCCS# function on U5/U8
(see bit-4 for select of U5 or U8 for MCCS#)
2
CHAS Enable (Pin V14)
0
Pin is defined as GPIOC.........................default
1
Pin is defined as CHAS
1
GPO12 Enable (Pin T5)
0
Pin is defined as XDIR...........................default
1
Pin is defined as GPO12
0
GPOWE# (GPO[23-16]) Enable (Pin T14)
0
Pin is defined as GPIOA ........................default
1
Pin is defined as GPOWE# (Rx74[2] also must
be set to 1)
Offset 77 – GPIO Control 4 Control................................RW
7
DRQ / DACK# Pins are GPI / GPO
0
Disable ...................................................default
1Enable
6
Game Port XY Pins are GPI / GPO
0
Disable ...................................................default
1Enable
5-4
Reserved
........................................ always reads 0
3
SERIRQ SMI Slot
0
Disable ...................................................default
1Enable
2
RTC Rx32 Write Protect
0
Disable ...................................................default
1Enable
1
RTC Rx0D Write Protect
0
Disable ...................................................default
1Enable
0
GPO13 Enable (Pin U5)
0
Pin defined as SOE#...............................default
1
Pin defined as GPO13
Offset 79-78 – PCS0# I/O Port Address.......................... RW
15-0 PCS0# I/O Port Address [15-0]
Offset 7B-7A – PCS1# I/O Port Address ........................ RW
15-0 PCS1# I/O Port Address [15-0]
Offset 7D-7C – PCI DMA Channel Enable .................... RW
15-9 Reserved
........................................ always reads 0
8
PCI DMA Pair A
0
Disable................................................... default
1Enable
7
PCI DMA Channel 7
0
Disable................................................... default
1Enable
6
PCI DMA Channel 6
0
Disable................................................... default
1Enable
5
PCI DMA Channel 5
0
Disable................................................... default
1Enable
4
Reserved
........................................ always reads 0
3
PCI DMA Channel 3
0
Disable................................................... default
1Enable
2
PCI DMA Channel 2
0
Disable................................................... default
1Enable
1
PCI DMA Channel 1
0
Disable................................................... default
1Enable
0
PCI DMA Channel 0
0
Disable................................................... default
1Enable
Offset 7F-7E – 32-Bit DMA Control ............................... RW
15-3 32-Bit DMA High Page (A31-24) Registers IOBase
2-1
Reserved
........................................ always reads 0
0
32-Bit DMA
0
Disable................................................... default
1Enable
Offset 80 – Programmable Chip Select Mask ................ RW
7-4
PCS1# I/O Port Address Mask [3-0]
3-0
PCS0# I/O Port Address Mask [3-0]



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