CS5451A

12

DS635PP1

(50 ppm/°C drift) that can be used by connecting

the VREFOUT pin to the VREFIN pin of the de-

vice. If higher accuracy/stability is required, an ex-

ternal reference can be used.

3.8

Power Supply

The low, stable analog power consumption and su-

perior supply rejection of the CS5451A allow for

the use of a simple charge-pump negative supply

generator. The use of a negative supply alleviates

the need for level shifting of the analog inputs. The

CPD pin and capacitor C1 provide the necessary

analog supply current as shown in Figure 5. The

Schottky diodes D1 and D2 are chosen for their low

forward voltages and high-speed capabilities. The

capacitor C2 provides the required charge storage

and bypassing of the negative supply. The CPD

output signal provides the charge pump driver sig-

nal. The frequency of the charge pump driver sig-

nal is synchronous to XIN. The nominal average

frequency is 1 MHz. The level on the VA- pin is

fed back internally so that the CPD output will reg-

ulate the VA- level to -2/3 of VA+ level.

Note the value of C1 in Figure 5. The 40 nF value

is recommended when the input frequency present-

ed to the XIN pin is 4.00 MHz. If the user decides

to use an XIN frequency that is significantly differ-

ent than 4.00 MHz (if the XIN frequency is in-

creased/decreased by more than 5% of 4.00 MHz,

then it is recommended that the user should alter

the value of C1. The percentage change in the value

of C1 (with respect to a reference value of 40 nF)

should be inversely proportional to the percentage

change in the XIN frequency. For example, if the

XIN frequency is increased from 4.00 MHz to

4.5 MHz, this represents a percentage increase of

12.5%. Therefore, the value of C1 should be re-

duced by 12.5%, making the new value for C1 to be

35 nF. For more information about the operation of

this type of charge pump circuit, the reader can re-

fer to Cirrus Logic, Inc.’s application note AN152:

Using the CS5521/24/28, and CS5525/26 Charge

Pump Drive for External Loads.

3.9

PCB Layout

For optimal performance, the CS5451A should be

placed entirely over an analog ground plane with

both the VA- and DGND pins of the device con-

nected to the analog plane. Place the analog-digital

plane split immediately adjacent to the digital por-

tion of the chip.

Note:

Refer to the CDB5451 Evaluation Board for

suggested layout details and Applications

Note 18 for more detailed layout guidelines.

Before layout, please call for our Free

Schematic Review Service.

AG N D

BA T 8 5

D1

C1

40 n F

C2

CPD

VA -

BAT 8 5

1µ F

D2

Figure 5. Generating VA- with a Charge Pump