DAC6571IDBVT datasheet(17/22 Pages) TI

17 / 22 page

www.ti.com

DAC6571 I

2C Update Sequence

Address Byte

Broadcast Address Byte

Control - Most Significant Byte

Least Significant Byte

DAC6571

SLAS406 – DECEMBER 2003

THEORY OF OPERATION (continued)

The DAC6571 requires a start condition, a valid I2C address, a control-MSB byte, and an LSB byte for a single

update. After the receipt of each byte, DAC6571 acknowledges by pulling the SDA line low during the high period

of a single clock pulse. A valid I2C address selects the DAC6571. The CTRL/MSB byte sets the operational

mode of the DAC6571, and the 4 most significant bits. The DAC6571 then receives the LSB byte containing 6

least significant data bits. DAC6571 performs an update on the falling edge of the acknowledge signal that

follows the LSB byte.

For the first update, DAC6571 requires a start condition, a valid I2C address, a CTRL/MSB byte, an LSB byte.

For all consecutive updates, DAC6571 needs a CTRL/MSB byte, and an LSB byte.

Using the I2C high-speed mode (fscl= 3.4 MHz), the clock running at 3.4 MHz, each 10-bit DAC update other than

the first update can be done within 18 clock cycles (CTRL/MSB byte, acknowledge signal, LSB byte,

acknowledge signal), at 188.88 KSPS. Using the fast mode (fscl= 400 kHz), clock running at 400 kHz, maximum

DAC update rate is limited to 22.22 KSPS. Once a stop condition is received, DAC6571 releases the I2C bus and

awaits a new start condition.

MSB

LSB

The address byte is the first byte received following the START condition from the master device. The first six

bits (MSBs) of the address are factory preset to 100110. The next bit of the address is the device select bit A0.

The A0 address input can be connected to VDD or digital GND, or can be actively driven by TTL/CMOS logic

levels. The device address is set by the state of this pin during the power-up sequence of the DAC6571. Up to 2

devices (DAC6571) can be connected to the same I2C-Bus without requiring additional glue logic.

MSB

LSB

Broadcast addressing is also supported by DAC6571. Broadcast addressing can be used for synchronously

updating or powering down multiple DAC6571 devices. Using the broadcast address, DAC6571 responds

regardless of the state of the address pin A0.

Most Significant Byte CTRL/MSB[7:0] consists of two zeros, two power-down bits, and four most significant bits

of 10-bit unsigned binary D/A conversion data.

Least Significant Byte LSB[7:0] consists of the 6 least significant bits of the 10-bit unsigned binary D/A

conversion data, followed by 2 don't care bits. DAC6571 updates at the falling edge of the acknowledge signal

that follows the LSB[0] bit.

DAC6571IDBVT 数据表(PDF) 17 Page - Texas Instruments

DAC6571IDBVT 数据表(HTML) 17 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

数据表下载