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LXT381II 数据表(PDF) 21 Page - Intel Corporation

部件名 LXT381II
功能描述  Octal E1 Line Interface Unit
PDF  36 Pages
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制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
标志 INTEL - Intel Corporation

LXT381II 数据表(HTML) 21 Page - Intel Corporation

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Octal E1 Line Interface — LXT381
Datasheet
21
3.3.1
Boundary Scan Register (BSR)
The BSR is a shift register that provides access to all the digital I/O pins. The BSR is used to apply
and read test patterns to/from the board. Each pin is associated with a scan cell in the BSR register.
Bidirectional pins or tristatable pins require more than one position in the register. Table 4 shows
the BSR scan cells and their functions. Data into the BSR is shifted in LSB first
.
Table 4.
Boundary Scan Register (BSR)
Bit #
Pin
Signal
I/O
Type
Bit
Symbol
Comments
0LOOP0
I/O
PDO0
1
LOOP0
I/O
PADD0
2LOOP1
I/O
PDO1
3LOOP1
I/O
PADI1
4LOOP2
I/O
PDO2
5LOOP2
I/O
PADI2
6LOOP3
I/O
PDO3
7LOOP3
I/O
PADI3
8LOOP4
I/O
PDO4
9LOOP4
I/O
PADI4
10
LOOP5
I/O
PDO5
11
LOOP5
I/O
PADI5
12
LOOP6
I/O
PDO6
13
LOOP6
I/O
PADI6
14
LOOP7
I/O
PDO7
15
LOOP7
I/O
PADI7
16
N/A
-
PDOEN
PDOEN controls the LOOP0 through LOOP7 pins.
Setting PDOEN to “1” configures the pins as outputs. The output value to
the pin is set in PDO[0..7].
Setting PDOEN to “0” tristates all the pins. The input value to the pins can
be read in PADD[0.7].
17
TCLK1
I
TCLK1
18
TPOS1
I
TPOS1
19
TNEG1
I
TNEG1
20
RCLK1
O
RCLK1
21
RPOS1
O
RPOS1
22
RNEG1
O
RNEG1
23
N/A
-
HIZB1
HIZB1 controls the RPOS1, RNEG1 and RCLK1 pins. Setting HIZB1 to
“1” enables output on the pins. Setting HIZB1 to “0” tristates the pins.
24
LOS1
O
LOS1
25
TCLK0
I
TCLK0
26
TPOS0
I
TPOS0
27
TNEG0
I
TNEG0



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