ICS308

MDS 308 F

1

Revision 090704

Description

The ICS308 is a versatile serially programmable, quad

PLL clock source. The ICS308 can generate any

frequency from 250 kHz to 200 MHz, and up to 6

different output frequencies simultaneously. The

outputs can be reprogrammed on the fly, and will lock to

a new frequency in 10 ms or less. Smooth transitions

(in which the clock duty cycle remains roughly 50%) are

guaranteed if the output divider is not changed.

The device includes a PDTS pin which tri-states the

output clocks and powers down the entire chip.

The ICS308 default for non-programmed start-up are

buffered reference clock outputs on all clock output

pins.

Features

frequency via a 3-wire interface

Block Diagram

C rystal

O scillator

GN D

2

3

VDD

PDT S

PLL2

PLL3

Divide

Logic

and

Output

Enable

Control

SCLK

DATA

CLK1

CLK9

CLK8

CLK7

CLK6

CLK5

CLK4

CLK3

CLK2

PLL4

PLL1

X2

Cry stal or

cloc k input

E xternal capacitors are

required w ith a crystal input.

X 1/IC LK

STROBE