LAN83C185 datasheet(21/61 Pages) SMSC

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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)

Datasheet

SMSC LAN83C185

Rev. 0.8 (11-16-04)

DATASHEET

4.3.4

Descrambling

The descrambler performs an inverse function to the scrambler in the transmitter and also performs

the Serial In Parallel Out (SIPO) conversion of the data.

During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to the

incoming stream. Once synchronization is achieved, the descrambler locks on this key and is able to

descramble incoming data.

Special logic in the descrambler ensures synchronization with the remote PHY by searching for IDLE

symbols within a window of 4000 bytes (40us). This window ensures that a maximum packet size of

1514 bytes, allowed by the IEEE 802.3 standard, can be received with no interference. If no IDLE-

symbols are detected within this time-period, receive operation is aborted and the descrambler re-starts

the synchronization process.

The descrambler can be bypassed by setting bit 0 of register 31.

4.3.5

Alignment

The de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /J/K/ Start-of-Stream

Delimiter (SSD) pair at the start of a packet. Once the code-word alignment is determined, it is stored

and utilized until the next start of frame.

4.3.6

5B/4B Decoding

The 5-bit code-groups are translated into 4-bit data nibbles according to the 4B/5B table. The

translated data is presented on the RXD[3:0] signal lines. The SSD, /J/K/, is translated to “0101 0101”

as the first 2 nibbles of the MAC preamble. Reception of the SSD causes the PHY to assert the RX_DV

signal, indicating that valid data is available on the RXD bus. Successive valid code-groups are

translated to data nibbles. Reception of either the End of Stream Delimiter (ESD) consisting of the /T/R/

symbols, or at least two /I/ symbols causes the PHY to de-assert carrier sense and RX_DV.

These symbols are not translated into data.

The decoding process may be bypassed by clearing bit 6 of register 31. When the decoding is

bypassed the 5th receive data bit is driven out on RX_ER/RXD4. Decoding may be bypassed only

when the MAC interface is in MII mode.

4.3.7

Receive Data Valid Signal

The Receive Data Valid signal (RX_DV) indicates that recovered and decoded nibbles are being

presented on the RXD[3:0] outputs synchronous to RX_CLK. RX_DV becomes active after the /J/K/

delimiter has been recognized and RXD is aligned to nibble boundaries. It remains active until either

the /T/R/ delimiter is recognized or link test indicates failure or SIGDET becomes false.

RX_DV is asserted when the first nibble of translated /J/K/ is ready for transfer over the Media

Independent Interface (MII).

Figure 4.3 Relationship Between Received Data and Some MII Signals

data data data data

RXD

RX_DV

RX_CLK

data data data data

CLEAR-TEXT

Idle

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