High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)

Datasheet

Rev. 0.8 (11-16-04)

6

SMSC LAN83C185

DATASHEET

List of Figures

Figure 1.1 LAN83C185 Architectural Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 2.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4.1 100Base-TX Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 4.2 Receive Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 4.3 Relationship Between Received Data and Some MII Signals . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 4.4 MDIO Timing and Frame Structure - READ Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 4.5 MDIO Timing and Frame Structure - WRITE Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 5.1 PHY Address Strapping on LEDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 7.1 64 Pin TQFP Package Outline, 10X10X1.4 Body, 2 MM Footprint . . . . . . . . . . . . . . . . . . . . 61