R0 REGISTER

The R0 register address bits (R0 [1:0]) are “00”.

The SPI_DEF bit selects between using the default IF counter values and user programmable values. The use of the default

counter values requires that only words R0 to R3 (registers R3, loaded first, to R0, loaded last) be sent after initial power up.

The RF_LD bit activates the lock detect output of the LD pin (pin 19). The lock detect mode shows the lock status of the RF PLL.

The waveform of the lock detect mode is shown in Figure 1,inthe Functional Description section on LOCK DETECT.

The SPUR_CRL bit is set to 1 only in the GPS mode with the LMX2532LQ1065 when a 19.68 MHz reference oscillator is used.

The RF N counter consists of the 4-bit programmable counter (RF_B counter), the 3-bit swallow counter (RF_A counter) and the

11-bit delta sigma modulator (RF_FN counter). The equations for calculating the counter values are presented below.

R0 REGISTER

MSB

SHIFT REGISTER BIT LOCATION

LSB

23

22

21

20

19

18

17

16

15

14

13

12

11

10

987654321

0

Data Field

Address

Field

R0

(Default)

SPI_

DEF

RF_

SEL

RF_

LD

SP

UR_

CRL

RF_B

[3:0]

RF_A

[2:0]

RF_FN

[10:0]

00

Name

Functions

SPI_DEF

Default Register Selection

0 = OFF (Use values set in R0 to R6)

1 = ON (Use default values set in R0 to R3)

RF_SEL

RF Select Configuration

See Table 8. RF_SEL Configuration below

RF_LD

RF Lock Detect

0 = Hard zero (GND)

1 = Lock detect

SPUR_CRL

Spur Control

1 = LMX2532LQ1065 in GPS mode with 19.68 MHz reference oscillator only

0 = All other options

RF_B [3:0]

RF_B Counter

4-bit programmable counter

2

≤ RF_B ≤ 15

RF_A [2:0]

RF_A Counter

3-bit swallow counter

0

≤ RF_A ≤ 7 for LMX2522

0

≤ RF_A ≤ 5 for LMX2532

RF_FN [10:0]

RF Fractional Numerator Counter

11-bit programmable counter

0

0

TABLE 8. RF_SEL Configuration

Device Type

RF_SEL = 0

RF_SEL = 1

LMX2522

GPS

K-PCS

LMX2532

K-Cellular

GPS

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