13/22

M68AF031A

Write Mode

The M68AF031A is in the Write mode whenever

the W and E are Low. Either the Chip Enable input

(E) or the Write Enable input (W) must be de-

asserted

during

Address

transitions

for

subsequent write cycles. When E (W) is Low, write

cycle begins on the W (E)'s falling edge.

Therefore, address setup time is referenced to

respectively, and is determined by the latter

occurring edge.

The Write cycle can be terminated by the earlier

rising edge of E or W.

If the Output is enabled (E = Low, G = Low), then

W will return the outputs to high impedance within

avoid bus contention in this type of operation. Data

edge of E, whichever occurs first, and remain valid

Figure 13. Write Enable Controlled, Write AC Waveforms

Note: 1. During this period DQ0-DQ7 are in output state and input signals should not be applied.

Figure 14. Chip Enable Controlled, Write AC Waveforms

AI05941

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A14

E

W

DQ0-DQ7

VALID

tAVWH

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

tELWH

AI05942

tAVAV

tEHAX

tDVEH

A0-A14

E

W

DQ0-DQ7

VALID

tAVEH

tAVEL

tELEH

tEHDX

DATA INPUT

tWLEH