MPC8271VR datasheet(13/56 Pages) MOTOROLA

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MOTOROLA

MPC8272 PowerQUICC II™ Family Hardware Speciﬁcations

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Thermal Characteristics

4.5

Experimental Determination

To determine the junction temperature of the device in the application after prototypes are available, the

thermal characterization parameter (

JT) can be used to determine the junction temperature with a

measurement of the temperature at the top center of the package case using the following equation:

TJ = TT + (ΨJT × PD)

where:

JT = thermal characterization parameter

TT = thermocouple temperature on top of package

PD = power dissipation in package

The thermal characterization parameter is measured per JEDEC JESD51-2 speciﬁcation using a 40 gauge

type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned

so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the

thermocouple junction and over 1 mm of wire extending from the junction. The thermocouple wire is placed

ﬂat against the case to avoid measurement errors caused by cooling effects of the thermocouple wire.

4.6

Layout Practices

Each VCC pin should be provided with a low-impedance path to the board’s power supply. Each ground pin

should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct

groups of logic on chip. The VCC power supply should be bypassed to ground using at least four 0.1 µF

bypass capacitors located as close as possible to the four sides of the package. The capacitor leads and

associated printed circuit traces connecting to chip VCC and ground should be kept to less than half an inch

per capacitor lead. A four-layer board employing two inner layers as VCC and GND planes is recommended.

All output pins on the MPC8272 have fast rise and fall times. Printed circuit (PC) trace interconnection

length should be minimized in order to minimize overdamped conditions and reﬂections caused by these

fast output switching times. This recommendation particularly applies to the address and data buses.

Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all

device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and

bypassing becomes especially critical in systems with higher capacitive loads because these loads create

higher transient currents in the VCC and GND circuits. Pull up all unused inputs or signals that will be inputs

during reset. Special care should be taken to minimize the noise levels on the PLL supply pins.

4.7

References

Semiconductor Equipment and Materials International

(415) 964-5111

805 East Middleﬁeld Rd.

Mountain View, CA 94043

MIL-SPEC and EIA/JESD (JEDEC) Speciﬁcations

800-854-7179 or

(Available from Global Engineering Documents)

303-397-7956

JEDEC Speciﬁcations

http://www.jedec.org

1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an

Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.

2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance

and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp.

212–220.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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