MPC8271VR datasheet(3/56 Pages) MOTOROLA

3 / 56 page

MOTOROLA

MPC8272 PowerQUICC II™ Family Hardware Speciﬁcations

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Overview

Figure 1. Block Diagram

1.1

Features

The major features of the MPC8272 are as follows:

•

Dual-issue integer (G2_LE) core

— A core version of the MPC603e microprocessor

— System core microprocessor supporting frequencies of 266-400 MHz

— Separate 16-Kbyte data and instruction caches:

– Four-way set associative

– Physically addressed

– LRU replacement algorithm

— PowerPC architecture-compliant memory management unit (MMU)

— Common on-chip processor (COP) test interface

— Supports bus snooping for cache coherency

— Floating-point unit (FPU) supports ﬂoating-point arithmetic

— Support for cache locking

•

Low-power consumption

•

Separate power supply for internal logic (1.5 V) and for I/O (3.3 V)

16 Kbytes

G2_LE Core

I-Cache

I-MMU

16 Kbytes

D-Cache

D-MMU

Communication Processor Module (CPM)

Timers

Parallel I/O

Baud Rate

Generators

32-bit RISC Microcontroller

and Program ROM

Serial

DMA

60x-to-PCI

Bridge

Memory Controller

Clock Counter

System Functions

System Interface Unit

(SIU)

PCI Bus

32 bits, up to 66 MHz

FCC1

FCC2

SCC1

SCC3

SCC4

SMC1

SMC2

SPI

I2C

Serial Interface

2 MII/RMII

Port

Ports

60x Bus

Interrupt

Controller

Time Slot Assigner

2 TDM Ports

Non-Multiplexed

I/O

Bus Interface Unit

Virtual

IDMAs

16 KB

Security (SEC) 1

1 8-bit Utopia

Serial interface

4 KB

Instruction

RAM

Data

RAM

Note

1 MPC8272/8248 only

2 MPC8272/8271 only

USB 2.0

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MPC8271VR 数据表(PDF) 3 Page - Motorola, Inc

MPC8271VR 数据表(HTML) 3 Page - Motorola, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

数据表下载