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SAF7118H 数据表(PDF) 66 Page - NXP Semiconductors

部件名 SAF7118H
功能描述  Multistandard video decoder with adaptive comb filter and component video input
PDF  173 Pages
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

SAF7118H 数据表(HTML) 66 Page - NXP Semiconductors

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2004 Jul 22
66
Philips Semiconductors
Product specification
Multistandard video decoder with adaptive
comb filter and component video input
SAF7118
Table 21 Bytes stream of the data slicer
Notes
1. NEP = inverted EP (see note 2).
2. EP = Even Parity of bits D5 to D0.
3. FID = 0: field 1; FID = 1: field 2.
4. I1 = 0 and I0 = 0: before line 1; I1 = 0 and I0 = 1: lines 1 to 23; I1 = 1 and I0 = 0: after line 23; I1 = 1 and I0 = 1:
line 24 to end of field.
5. Subaddress 5DH at 3EH and 3FH are used for ITU 656 like SAV/EAV header generation; recommended value.
6. V = 0: active video; V = 1: blanking.
7. H = 0: start of line; H = 1: end of line.
8. DC = Data Count in Dwords according to the data type.
9. OP = Odd Parity of bits D6 to D0.
10. LN = Line Number.
11. DT = Data Type according to table.
NICK
NAME
COMMENT
D7
D6
D5
D4
D3
D2
D1
D0
DID,
SAV,
EAV
subaddress
5DH = 00H
NEP(1)
EP(2)
0
1
0
FID(3)
I1(4)
I0(4)
subaddress 5DH;
D5 = 1
NEP(1)
EP(2)
0
D4[5DH] D3[5DH] D2[5DH] D1[5DH] D0[5DH]
subaddress 5DH
D5 = 3EH; note 5
1
FID(3)
V(6)
H(7)
P3
P2
P1
P0
subaddress 5DH
D5 = 3FH; note 5
0
FID(3)
V(6)
H(7)
P3
P2
P1
P0
SDID
programmable via
subaddress 5EH
NEP(1)
EP(2)
D5[5EH]
D4[5EH]
D3[5EH]
D2[5EH]
D1[5EH]
D0[5EH]
DC(8)
NEP(1)
EP(2)
DC5
DC4
DC3
DC2
DC1
DC0
IDI1
OP(9)
FID(3)
LN8(10)
LN7(10)
LN6(10)
LN5(10)
LN4(10)
LN3(10)
IDI2
OP(9)
LN2(10)
LN1(10)
LN0(10)
DT3(11)
DT2(11)
DT1(11)
DT0(11)
CS
check sum byte
CS6
CS6
CS5
CS4
CS3
CS2
CS1
CS0
BC
valid byte count
OP(9)
0
CNT5
CNT4
CNT3
CNT2
CNT1
CNT0



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